From 2ab3e5e99ce4c5a9c59214c994605bb150e8679d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 20 Apr 2019 22:36:49 +0100 Subject: [PATCH] add __iter__ to several classes, add global shape() function use in FIFOControl --- src/add/fpbase.py | 11 +++++++++++ src/add/fpcommon/denorm.py | 8 ++++++++ src/add/fpcommon/pack.py | 6 +++++- src/add/fpcommon/postcalc.py | 7 +++++++ src/add/singlepipe.py | 16 +++++++++++++--- src/add/test_inout_mux_pipe.py | 8 +++++--- src/add/test_outmux_pipe.py | 14 +++++++++----- 7 files changed, 58 insertions(+), 12 deletions(-) diff --git a/src/add/fpbase.py b/src/add/fpbase.py index c53cabbb..66cc8c0e 100644 --- a/src/add/fpbase.py +++ b/src/add/fpbase.py @@ -145,6 +145,11 @@ class FPNumBase: def _is_denormalised(self): return (self.exp_n126) & (self.m_msbzero) + def __iter__(self): + yield self.s + yield self.e + yield self.m + def eq(self, inp): return [self.s.eq(inp.s), self.e.eq(inp.e), self.m.eq(inp.m)] @@ -541,6 +546,12 @@ class Overflow: self.roundz = Signal(reset_less=True) + def __iter__(self): + yield self.guard + yield self.round_bit + yield self.sticky + yield self.m0 + def eq(self, inp): return [self.guard.eq(inp.guard), self.round_bit.eq(inp.round_bit), diff --git a/src/add/fpcommon/denorm.py b/src/add/fpcommon/denorm.py index 64d4b433..9fbbc976 100644 --- a/src/add/fpcommon/denorm.py +++ b/src/add/fpcommon/denorm.py @@ -20,6 +20,14 @@ class FPSCData: self.out_do_z = Signal(reset_less=True) self.mid = Signal(id_wid, reset_less=True) + def __iter__(self): + yield from self.a + yield from self.b + yield from self.z + yield self.oz + yield self.out_do_z + yield self.mid + def eq(self, i): return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz), self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)] diff --git a/src/add/fpcommon/pack.py b/src/add/fpcommon/pack.py index 512be000..0f75d46c 100644 --- a/src/add/fpcommon/pack.py +++ b/src/add/fpcommon/pack.py @@ -16,11 +16,15 @@ class FPPackData: self.z = Signal(width, reset_less=True) self.mid = Signal(id_wid, reset_less=True) + def __iter__(self): + yield self.z + yield self.mid + def eq(self, i): return [self.z.eq(i.z), self.mid.eq(i.mid)] def ports(self): - return [self.z, self.mid] + return list(self) class FPPackMod: diff --git a/src/add/fpcommon/postcalc.py b/src/add/fpcommon/postcalc.py index f428603d..7111dc8a 100644 --- a/src/add/fpcommon/postcalc.py +++ b/src/add/fpcommon/postcalc.py @@ -14,6 +14,13 @@ class FPAddStage1Data: self.of = Overflow() self.mid = Signal(id_wid, reset_less=True) + def __iter__(self): + yield from self.z + yield self.out_do_z + yield self.oz + yield from self.of + yield self.mid + def eq(self, i): return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz), self.of.eq(i.of), self.mid.eq(i.mid)] diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py index 88709ffc..52decdbb 100644 --- a/src/add/singlepipe.py +++ b/src/add/singlepipe.py @@ -466,6 +466,16 @@ def eq(o, i): return res +def shape(i): + print ("shape", i) + r = 0 + for part in list(i): + print ("shape?", part) + s, _ = part.shape() + r += s + return r, False + + def cat(i): """ flattens a compound structure recursively using Cat """ @@ -698,6 +708,8 @@ class ControlBase: """ handles case where stage has dynamic ready/valid functions """ m = Module() + m.submodules.p = self.p + m.submodules.n = self.n if self.stage is not None and hasattr(self.stage, "setup"): self.stage.setup(m, self.p.i_data) @@ -1176,7 +1188,7 @@ class FIFOControl(ControlBase): self.m = m = ControlBase._elaborate(self, platform) # make a FIFO with a signal of equal width to the o_data. - (fwidth, _) = self.n.o_data.shape() + (fwidth, _) = shape(self.n.o_data) if self.buffered: fifo = SyncFIFOBuffered(fwidth, self.fdepth) else: @@ -1229,10 +1241,8 @@ class BufferedHandshake(FIFOControl): fwft=True, pipe=False) -""" # this is *probably* SimpleHandshake (note: memory cell size=0) class SimpleHandshake(FIFOControl): def __init__(self, stage, in_multi=None, stage_ctl=False): FIFOControl.__init__(self, 0, stage, in_multi, stage_ctl, fwft=True, pipe=False) -""" diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py index 92b6f53f..a737ddf2 100644 --- a/src/add/test_inout_mux_pipe.py +++ b/src/add/test_inout_mux_pipe.py @@ -22,8 +22,10 @@ class PassData: # (Value): self.idx = Signal(8, reset_less=True) self.data = Signal(16, reset_less=True) - def _rhs_signals(self): - return self.ports() + def __iter__(self): + yield self.mid + yield self.idx + yield self.data def shape(self): bits, sign = 0, False @@ -36,7 +38,7 @@ class PassData: # (Value): return [self.mid.eq(i.mid), self.idx.eq(i.idx), self.data.eq(i.data)] def ports(self): - return [self.mid, self.idx, self.data] + return list(self) class PassThroughStage: diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py index 7c25f384..f1b0774f 100644 --- a/src/add/test_outmux_pipe.py +++ b/src/add/test_outmux_pipe.py @@ -5,7 +5,7 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil from multipipe import CombMuxOutPipe -from singlepipe import SimpleHandshake +from singlepipe import SimpleHandshake, PassThroughHandshake class PassInData: @@ -13,6 +13,10 @@ class PassInData: self.mid = Signal(2, reset_less=True) self.data = Signal(16, reset_less=True) + def __iter__(self): + yield self.mid + yield self.data + def eq(self, i): return [self.mid.eq(i.mid), self.data.eq(i.data)] @@ -43,9 +47,9 @@ class PassThroughDataStage: -class PassThroughPipe(SimpleHandshake): +class PassThroughPipe(PassThroughHandshake): def __init__(self): - SimpleHandshake.__init__(self, PassThroughDataStage()) + PassThroughHandshake.__init__(self, PassThroughDataStage()) @@ -233,8 +237,8 @@ class TestSyncToPriorityPipe: def elaborate(self, platform): m = Module() - m.submodules += self.pipe - m.submodules += self.muxpipe + m.submodules.pipe = self.pipe + m.submodules.muxpipe = self.muxpipe m.d.comb += self.pipe.n.connect_to_next(self.muxpipe.p) return m -- 2.30.2