From 2abe38d25bf6d2ad1927a2de739521e0a55fd9a9 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 19 Mar 2021 14:12:44 +0000
Subject: [PATCH] code-shuffle in TestIssuer, split out setting up peripherals

---
 src/soc/simple/issuer.py | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 872e2e95..ba9caca0 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -520,8 +520,7 @@ class TestIssuerInternal(Elaboratable):
                         comb += self.insn_done.eq(1)
                         m.next = "INSN_START"  # back to fetch
 
-    def elaborate(self, platform):
-        m = Module()
+    def setup_peripherals(self, m):
         comb, sync = m.d.comb, m.d.sync
 
         m.submodules.core = core = DomainRenamer("coresync")(self.core)
@@ -596,6 +595,20 @@ class TestIssuerInternal(Elaboratable):
         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 
+        return core_rst
+
+    def elaborate(self, platform):
+        m = Module()
+        # convenience
+        comb, sync = m.d.comb, m.d.sync
+        cur_state = self.cur_state
+        pdecode2 = self.pdecode2
+        dbg = self.dbg
+        core = self.core
+
+        # set up peripherals and core
+        core_rst = self.setup_peripherals(m)
+
         # PC and instruction from I-Memory
         comb += self.pc_o.eq(cur_state.pc)
         pc_changed = Signal() # note write to PC
-- 
2.30.2