From 2aceac3ea760fb648a01b51c5d7cecf3eaebbaa2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 3 Apr 2023 11:00:26 +0100 Subject: [PATCH] add architectural note about UnVectorised --- openpower/sv/svp64.mdwn | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 57b54d7f3..d47dc8fe8 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -124,6 +124,15 @@ Any operation that inherently makes no sense if repeated is termed which have no registers. `mtmsr` is also classed as UnVectoriseable because there is only one `MSR`. +UnVectorised instructions are required to be detected as such if +Prefixed (either SVP64 or SVP64Single) and an Illegal Instruction +Trap raised. + +*Architectural Note: Given that a "pre-classification" Decode Phase is +required (identifying whether the Suffix - Defined Word - is +Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional), +adding "UnVectorised" to this phase is not unreasonable.* + ## Register files, elements, and Element-width Overrides In the Upper Compliancy Levels of SVP64 the size of the GPR and FPR -- 2.30.2