From 2ae21bd133c357fcd7b6e06dc7d7d9e0660abe2c Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 15 Aug 2019 08:34:40 +0000 Subject: [PATCH] [AArch64] Remove unneeded FSUB alternatives and add a new one The floating-point subtraction patterns don't need to handle subtraction of constants, since those go through the addition patterns instead. There was a missing MOVPRFX alternative for FSUBR though. 2019-08-15 Richard Sandiford gcc/ * config/aarch64/aarch64-sve.md (*sub3): Remove immediate FADD and FSUB alternatives. Add a MOVPRFX alternative for FSUBR. From-SVN: r274514 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/aarch64-sve.md | 25 +++++++++++-------------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6bfbd9976df..62376a5f43f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-08-15 Richard Sandiford + + * config/aarch64/aarch64-sve.md (*sub3): Remove immediate + FADD and FSUB alternatives. Add a MOVPRFX alternative for FSUBR. + 2019-08-15 Richard Sandiford Kugan Vivekanandarajah diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index c4e46025903..fa7f899bd9d 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -2878,34 +2878,31 @@ ;; ---- [FP] Subtraction ;; ------------------------------------------------------------------------- ;; Includes: -;; - FADD ;; - FSUB ;; - FSUBR ;; ------------------------------------------------------------------------- ;; Predicated floating-point subtraction. (define_insn_and_split "*sub3" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w, w, w") + [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl, Upl, Upl") - (match_operand:SI 4 "aarch64_sve_gp_strictness" "i, i, i, Z") - (match_operand:SVE_F 2 "aarch64_sve_float_arith_operand" "0, 0, vsA, w") - (match_operand:SVE_F 3 "aarch64_sve_float_arith_with_sub_operand" "vsA, vsN, 0, w")] + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (match_operand:SI 4 "aarch64_sve_gp_strictness" "i, Z, i") + (match_operand:SVE_F 2 "aarch64_sve_float_arith_operand" "vsA, w, vsA") + (match_operand:SVE_F 3 "register_operand" "0, w, 0")] UNSPEC_COND_FSUB))] - "TARGET_SVE - && (register_operand (operands[2], mode) - || register_operand (operands[3], mode))" + "TARGET_SVE" "@ - fsub\t%0., %1/m, %0., #%3 - fadd\t%0., %1/m, %0., #%N3 fsubr\t%0., %1/m, %0., #%2 - #" + # + movprfx\t%0, %3\;fsubr\t%0., %1/m, %0., #%2" ; Split the unpredicated form after reload, so that we don't have ; the unnecessary PTRUE. "&& reload_completed - && register_operand (operands[2], mode) - && register_operand (operands[3], mode)" + && register_operand (operands[2], mode)" [(set (match_dup 0) (minus:SVE_F (match_dup 2) (match_dup 3)))] + "" + [(set_attr "movprfx" "*,*,yes")] ) ;; Predicated floating-point subtraction from a constant, merging with the -- 2.30.2