From 2ae7dec5300bb61a90842fefb1e846cd9f667a9e Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Mon, 9 Sep 2019 08:33:26 +0300 Subject: [PATCH] Add tests for Xilinx UG901 examples --- Makefile | 1 + tests/xilinx_ug901/asym_ram_sdp_read_wider.v | 74 +++++++++++ tests/xilinx_ug901/asym_ram_sdp_read_wider.ys | 22 ++++ tests/xilinx_ug901/asym_ram_sdp_write_wider.v | 75 +++++++++++ .../xilinx_ug901/asym_ram_sdp_write_wider.ys | 31 +++++ tests/xilinx_ug901/asym_ram_tdp_read_first.v | 85 ++++++++++++ tests/xilinx_ug901/asym_ram_tdp_read_first.ys | 21 +++ tests/xilinx_ug901/asym_ram_tdp_write_first.v | 92 +++++++++++++ .../xilinx_ug901/asym_ram_tdp_write_first.ys | 29 +++++ tests/xilinx_ug901/black_box_1.v | 19 +++ tests/xilinx_ug901/black_box_1.ys | 15 +++ tests/xilinx_ug901/bytewrite_ram_1b.v | 42 ++++++ tests/xilinx_ug901/bytewrite_ram_1b.ys | 22 ++++ tests/xilinx_ug901/bytewrite_tdp_ram_nc.v | 78 +++++++++++ tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys | 22 ++++ .../bytewrite_tdp_ram_readfirst2.v | 71 ++++++++++ .../bytewrite_tdp_ram_readfirst2.ys | 21 +++ tests/xilinx_ug901/bytewrite_tdp_ram_rf.v | 61 +++++++++ tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys | 21 +++ tests/xilinx_ug901/bytewrite_tdp_ram_wf.v | 68 ++++++++++ tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys | 23 ++++ tests/xilinx_ug901/cmacc.v | 122 ++++++++++++++++++ tests/xilinx_ug901/cmacc.ys | 25 ++++ tests/xilinx_ug901/cmult.v | 71 ++++++++++ tests/xilinx_ug901/cmult.ys | 31 +++++ .../xilinx_ug901/dynamic_shift_registers_1.v | 21 +++ .../xilinx_ug901/dynamic_shift_registers_1.ys | 15 +++ tests/xilinx_ug901/dynpreaddmultadd.v | 47 +++++++ tests/xilinx_ug901/dynpreaddmultadd.ys | 31 +++++ tests/xilinx_ug901/fsm_1.v | 42 ++++++ tests/xilinx_ug901/fsm_1.ys | 16 +++ tests/xilinx_ug901/latches.v | 17 +++ tests/xilinx_ug901/latches.ys | 10 ++ tests/xilinx_ug901/macc.v | 47 +++++++ tests/xilinx_ug901/macc.ys | 23 ++++ tests/xilinx_ug901/mult_unsigned.v | 33 +++++ tests/xilinx_ug901/mult_unsigned.ys | 29 +++++ tests/xilinx_ug901/presubmult.v | 43 ++++++ tests/xilinx_ug901/presubmult.ys | 23 ++++ .../xilinx_ug901/ram_simple_dual_one_clock.v | 25 ++++ .../xilinx_ug901/ram_simple_dual_one_clock.ys | 20 +++ .../xilinx_ug901/ram_simple_dual_two_clocks.v | 30 +++++ .../ram_simple_dual_two_clocks.ys | 20 +++ tests/xilinx_ug901/rams_dist.v | 24 ++++ tests/xilinx_ug901/rams_dist.ys | 21 +++ tests/xilinx_ug901/rams_init_file.data | 64 +++++++++ tests/xilinx_ug901/rams_init_file.v | 24 ++++ tests/xilinx_ug901/rams_init_file.ys | 22 ++++ tests/xilinx_ug901/rams_pipeline.v | 42 ++++++ tests/xilinx_ug901/rams_pipeline.ys | 22 ++++ tests/xilinx_ug901/rams_sp_nc.v | 26 ++++ tests/xilinx_ug901/rams_sp_nc.ys | 22 ++++ tests/xilinx_ug901/rams_sp_rf.v | 26 ++++ tests/xilinx_ug901/rams_sp_rf.ys | 22 ++++ tests/xilinx_ug901/rams_sp_rf_rst.v | 29 +++++ tests/xilinx_ug901/rams_sp_rf_rst.ys | 28 ++++ tests/xilinx_ug901/rams_sp_rom.v | 46 +++++++ tests/xilinx_ug901/rams_sp_rom.ys | 22 ++++ tests/xilinx_ug901/rams_sp_rom_1.v | 53 ++++++++ tests/xilinx_ug901/rams_sp_rom_1.ys | 22 ++++ tests/xilinx_ug901/rams_sp_wf.v | 26 ++++ tests/xilinx_ug901/rams_sp_wf.ys | 26 ++++ tests/xilinx_ug901/rams_tdp_rf_rf.v | 33 +++++ tests/xilinx_ug901/rams_tdp_rf_rf.ys | 21 +++ tests/xilinx_ug901/registers_1.v | 25 ++++ tests/xilinx_ug901/registers_1.ys | 12 ++ tests/xilinx_ug901/run-test.sh | 20 +++ tests/xilinx_ug901/sfir_shifter.v | 19 +++ tests/xilinx_ug901/sfir_shifter.ys | 16 +++ tests/xilinx_ug901/shift_registers_0.v | 22 ++++ tests/xilinx_ug901/shift_registers_0.ys | 13 ++ tests/xilinx_ug901/shift_registers_1.v | 24 ++++ tests/xilinx_ug901/shift_registers_1.ys | 14 ++ tests/xilinx_ug901/squarediffmacc.v | 52 ++++++++ tests/xilinx_ug901/squarediffmacc.ys | 23 ++++ tests/xilinx_ug901/squarediffmult.v | 42 ++++++ tests/xilinx_ug901/squarediffmult.ys | 30 +++++ tests/xilinx_ug901/top_mux.v | 18 +++ tests/xilinx_ug901/top_mux.ys | 13 ++ tests/xilinx_ug901/tristates_1.v | 17 +++ tests/xilinx_ug901/tristates_1.ys | 13 ++ tests/xilinx_ug901/tristates_2.v | 10 ++ tests/xilinx_ug901/tristates_2.ys | 13 ++ .../xilinx_ultraram_single_port_no_change.v | 78 +++++++++++ .../xilinx_ultraram_single_port_no_change.ys | 25 ++++ .../xilinx_ultraram_single_port_read_first.v | 78 +++++++++++ .../xilinx_ultraram_single_port_read_first.ys | 24 ++++ .../xilinx_ultraram_single_port_write_first.v | 82 ++++++++++++ ...xilinx_ultraram_single_port_write_first.ys | 24 ++++ 89 files changed, 2962 insertions(+) create mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.v create mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.ys create mode 100644 tests/xilinx_ug901/asym_ram_sdp_write_wider.v create mode 100644 tests/xilinx_ug901/asym_ram_sdp_write_wider.ys create mode 100644 tests/xilinx_ug901/asym_ram_tdp_read_first.v create mode 100644 tests/xilinx_ug901/asym_ram_tdp_read_first.ys create mode 100644 tests/xilinx_ug901/asym_ram_tdp_write_first.v create mode 100644 tests/xilinx_ug901/asym_ram_tdp_write_first.ys create mode 100644 tests/xilinx_ug901/black_box_1.v create mode 100644 tests/xilinx_ug901/black_box_1.ys create mode 100644 tests/xilinx_ug901/bytewrite_ram_1b.v create mode 100644 tests/xilinx_ug901/bytewrite_ram_1b.ys create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_nc.v create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_rf.v create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_wf.v create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys create mode 100644 tests/xilinx_ug901/cmacc.v create mode 100644 tests/xilinx_ug901/cmacc.ys create mode 100644 tests/xilinx_ug901/cmult.v create mode 100644 tests/xilinx_ug901/cmult.ys create mode 100644 tests/xilinx_ug901/dynamic_shift_registers_1.v create mode 100644 tests/xilinx_ug901/dynamic_shift_registers_1.ys create mode 100644 tests/xilinx_ug901/dynpreaddmultadd.v create mode 100644 tests/xilinx_ug901/dynpreaddmultadd.ys create mode 100644 tests/xilinx_ug901/fsm_1.v create mode 100644 tests/xilinx_ug901/fsm_1.ys create mode 100644 tests/xilinx_ug901/latches.v create mode 100644 tests/xilinx_ug901/latches.ys create mode 100644 tests/xilinx_ug901/macc.v create mode 100644 tests/xilinx_ug901/macc.ys create mode 100644 tests/xilinx_ug901/mult_unsigned.v create mode 100644 tests/xilinx_ug901/mult_unsigned.ys create mode 100644 tests/xilinx_ug901/presubmult.v create mode 100644 tests/xilinx_ug901/presubmult.ys create mode 100644 tests/xilinx_ug901/ram_simple_dual_one_clock.v create mode 100644 tests/xilinx_ug901/ram_simple_dual_one_clock.ys create mode 100644 tests/xilinx_ug901/ram_simple_dual_two_clocks.v create mode 100644 tests/xilinx_ug901/ram_simple_dual_two_clocks.ys create mode 100644 tests/xilinx_ug901/rams_dist.v create mode 100644 tests/xilinx_ug901/rams_dist.ys create mode 100644 tests/xilinx_ug901/rams_init_file.data create mode 100644 tests/xilinx_ug901/rams_init_file.v create mode 100644 tests/xilinx_ug901/rams_init_file.ys create mode 100644 tests/xilinx_ug901/rams_pipeline.v create mode 100644 tests/xilinx_ug901/rams_pipeline.ys create mode 100644 tests/xilinx_ug901/rams_sp_nc.v create mode 100644 tests/xilinx_ug901/rams_sp_nc.ys create mode 100644 tests/xilinx_ug901/rams_sp_rf.v create mode 100644 tests/xilinx_ug901/rams_sp_rf.ys create mode 100644 tests/xilinx_ug901/rams_sp_rf_rst.v create mode 100644 tests/xilinx_ug901/rams_sp_rf_rst.ys create mode 100644 tests/xilinx_ug901/rams_sp_rom.v create mode 100644 tests/xilinx_ug901/rams_sp_rom.ys create mode 100644 tests/xilinx_ug901/rams_sp_rom_1.v create mode 100644 tests/xilinx_ug901/rams_sp_rom_1.ys create mode 100644 tests/xilinx_ug901/rams_sp_wf.v create mode 100644 tests/xilinx_ug901/rams_sp_wf.ys create mode 100644 tests/xilinx_ug901/rams_tdp_rf_rf.v create mode 100644 tests/xilinx_ug901/rams_tdp_rf_rf.ys create mode 100644 tests/xilinx_ug901/registers_1.v create mode 100644 tests/xilinx_ug901/registers_1.ys create mode 100755 tests/xilinx_ug901/run-test.sh create mode 100644 tests/xilinx_ug901/sfir_shifter.v create mode 100644 tests/xilinx_ug901/sfir_shifter.ys create mode 100644 tests/xilinx_ug901/shift_registers_0.v create mode 100644 tests/xilinx_ug901/shift_registers_0.ys create mode 100644 tests/xilinx_ug901/shift_registers_1.v create mode 100644 tests/xilinx_ug901/shift_registers_1.ys create mode 100644 tests/xilinx_ug901/squarediffmacc.v create mode 100644 tests/xilinx_ug901/squarediffmacc.ys create mode 100644 tests/xilinx_ug901/squarediffmult.v create mode 100644 tests/xilinx_ug901/squarediffmult.ys create mode 100644 tests/xilinx_ug901/top_mux.v create mode 100644 tests/xilinx_ug901/top_mux.ys create mode 100644 tests/xilinx_ug901/tristates_1.v create mode 100644 tests/xilinx_ug901/tristates_1.ys create mode 100644 tests/xilinx_ug901/tristates_2.v create mode 100644 tests/xilinx_ug901/tristates_2.ys create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.ys create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.v create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.ys create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.v create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.ys diff --git a/Makefile b/Makefile index 895cfbf89..ef02bc947 100644 --- a/Makefile +++ b/Makefile @@ -715,6 +715,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh + +cd tests/xilinx_ug901 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.v b/tests/xilinx_ug901/asym_ram_sdp_read_wider.v new file mode 100644 index 000000000..0716dffdc --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_read_wider.v @@ -0,0 +1,74 @@ +// Asymmetric port RAM +// Read Wider than Write. Read Statement in loop +//asym_ram_sdp_read_wider.v + +module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB); +parameter WIDTHA = 4; +parameter SIZEA = 1024; +parameter ADDRWIDTHA = 10; + +parameter WIDTHB = 16; +parameter SIZEB = 256; +parameter ADDRWIDTHB = 8; +input clkA; +input clkB; +input weA; +input enaA, enaB; +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +output [WIDTHB-1:0] doB; +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHB-1:0] readB; + +always @(posedge clkA) +begin + if (enaA) begin + if (weA) + RAM[addrA] <= diA; + end +end + + +always @(posedge clkB) +begin : ramread + integer i; + reg [log2RATIO-1:0] lsbaddr; + if (enaB) begin + for (i = 0; i < RATIO; i = i+1) begin + lsbaddr = i; + readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}]; + end + end +end +assign doB = readB; + +endmodule + diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys new file mode 100644 index 000000000..c63157cdf --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys @@ -0,0 +1,22 @@ +read_verilog asym_ram_sdp_read_wider.v +hierarchy -top asym_ram_sdp_read_wider +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_sdp_read_wider +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 2 t:BUFG +select -assert-count 1 t:LUT2 +select -assert-count 4 t:RAMB18E1 + +select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.v b/tests/xilinx_ug901/asym_ram_sdp_write_wider.v new file mode 100644 index 000000000..22d12d2ce --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_write_wider.v @@ -0,0 +1,75 @@ +// Asymmetric port RAM +// Write wider than Read. Write Statement in a loop. +// asym_ram_sdp_write_wider.v + +module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB); +parameter WIDTHB = 4; +//Default parameters were changed because of slow test +//parameter SIZEB = 1024; +//parameter ADDRWIDTHB = 10; +parameter SIZEB = 256; +parameter ADDRWIDTHB = 8; + +//parameter WIDTHA = 16; +parameter WIDTHA = 8; +parameter SIZEA = 256; +parameter ADDRWIDTHA = 8; +input clkA; +input clkB; +input weA; +input enaA, enaB; +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +output [WIDTHB-1:0] doB; +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHB-1:0] readB; + +always @(posedge clkB) begin + if (enaB) begin + readB <= RAM[addrB]; + end +end +assign doB = readB; + +always @(posedge clkA) +begin : ramwrite + integer i; + reg [log2RATIO-1:0] lsbaddr; + for (i=0; i< RATIO; i= i+ 1) begin : write1 + lsbaddr = i; + if (enaA) begin + if (weA) + RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; + end + end +end + +endmodule diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys new file mode 100644 index 000000000..229d98df6 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys @@ -0,0 +1,31 @@ +read_verilog asym_ram_sdp_write_wider.v +hierarchy -top asym_ram_sdp_write_wider +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_sdp_write_wider +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 2 t:BUFG +select -assert-count 1028 t:FDRE +select -assert-count 170 t:LUT2 +select -assert-count 6 t:LUT3 +select -assert-count 518 t:LUT4 +select -assert-count 10 t:LUT5 +select -assert-count 484 t:LUT6 +select -assert-count 157 t:MUXF7 +select -assert-count 3 t:MUXF8 + +#RRAM128X1D will be synthesized in case when the parameter WIDTHA=4 +#select -assert-count 8 t:RAM128X1D + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.v b/tests/xilinx_ug901/asym_ram_tdp_read_first.v new file mode 100644 index 000000000..2b807a382 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_read_first.v @@ -0,0 +1,85 @@ +// Asymetric RAM - TDP +// READ_FIRST MODE. +// asym_ram_tdp_read_first.v + + +module asym_ram_tdp_read_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB); +parameter WIDTHB = 4; +parameter SIZEB = 1024; +parameter ADDRWIDTHB = 10; +parameter WIDTHA = 16; +parameter SIZEA = 256; +parameter ADDRWIDTHA = 8; +input clkA; +input clkB; +input weA, weB; +input enaA, enaB; + +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +input [WIDTHB-1:0] diB; + +output [WIDTHA-1:0] doA; +output [WIDTHB-1:0] doB; + +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHA-1:0] readA; +reg [WIDTHB-1:0] readB; + +always @(posedge clkB) +begin + if (enaB) begin + readB <= RAM[addrB] ; + if (weB) + RAM[addrB] <= diB; + end +end + + +always @(posedge clkA) +begin : portA + integer i; + reg [log2RATIO-1:0] lsbaddr ; + for (i=0; i< RATIO; i= i+ 1) begin + lsbaddr = i; + if (enaA) begin + readA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}]; + + if (weA) + RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; + end + end +end + +assign doA = readA; +assign doB = readB; + +endmodule diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.ys b/tests/xilinx_ug901/asym_ram_tdp_read_first.ys new file mode 100644 index 000000000..5f96b800c --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_read_first.ys @@ -0,0 +1,21 @@ +read_verilog asym_ram_tdp_read_first.v +hierarchy -top asym_ram_tdp_read_first +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_tdp_read_first +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 1 t:$mem +select -assert-count 2 t:LUT2 + +select -assert-none t:$mem t:LUT2 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.v b/tests/xilinx_ug901/asym_ram_tdp_write_first.v new file mode 100644 index 000000000..90187ea26 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_write_first.v @@ -0,0 +1,92 @@ +// Asymmetric port RAM - TDP +// WRITE_FIRST MODE. +// asym_ram_tdp_write_first.v + + +module asym_ram_tdp_write_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB); +parameter WIDTHB = 4; +//Default parameters were changed because of slow test +//parameter SIZEB = 1024; +//parameter ADDRWIDTHB = 10; +parameter SIZEB = 32; +parameter ADDRWIDTHB = 8; + +//parameter WIDTHA = 16; +parameter WIDTHA = 4; +//parameter SIZEA = 256; +parameter SIZEA = 32; +parameter ADDRWIDTHA = 8; +input clkA; +input clkB; +input weA, weB; +input enaA, enaB; + +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +input [WIDTHB-1:0] diB; + +output [WIDTHA-1:0] doA; +output [WIDTHB-1:0] doB; + +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHA-1:0] readA; +reg [WIDTHB-1:0] readB; + +always @(posedge clkB) +begin + if (enaB) begin + if (weB) + RAM[addrB] = diB; + readB = RAM[addrB] ; + end +end + + +always @(posedge clkA) +begin : portA + integer i; + reg [log2RATIO-1:0] lsbaddr ; + for (i=0; i< RATIO; i= i+ 1) begin + lsbaddr = i; + if (enaA) begin + + if (weA) + RAM[{addrA, lsbaddr}] = diA[(i+1)*minWIDTH-1 -: minWIDTH]; + + readA[(i+1)*minWIDTH -1 -: minWIDTH] = RAM[{addrA, lsbaddr}]; + end + end +end + +assign doA = readA; +assign doB = readB; + +endmodule diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.ys b/tests/xilinx_ug901/asym_ram_tdp_write_first.ys new file mode 100644 index 000000000..bbe3cc849 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_write_first.ys @@ -0,0 +1,29 @@ +read_verilog asym_ram_tdp_write_first.v +hierarchy -top asym_ram_tdp_write_first +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_tdp_write_first +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 2 t:BUFG +select -assert-count 200 t:FDRE +select -assert-count 10 t:LUT2 +select -assert-count 44 t:LUT3 +select -assert-count 81 t:LUT4 +select -assert-count 104 t:LUT5 +select -assert-count 560 t:LUT6 +select -assert-count 261 t:MUXF7 +select -assert-count 127 t:MUXF8 + + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/xilinx_ug901/black_box_1.v b/tests/xilinx_ug901/black_box_1.v new file mode 100644 index 000000000..40caa1b10 --- /dev/null +++ b/tests/xilinx_ug901/black_box_1.v @@ -0,0 +1,19 @@ +// Black Box +// black_box_1.v +// +(* black_box *) module black_box1 (in1, in2, dout); +input in1, in2; +output dout; +endmodule + +module black_box_1 (DI_1, DI_2, DOUT); +input DI_1, DI_2; +output DOUT; + +black_box1 U1 ( + .in1(DI_1), + .in2(DI_2), + .dout(DOUT) + ); + +endmodule diff --git a/tests/xilinx_ug901/black_box_1.ys b/tests/xilinx_ug901/black_box_1.ys new file mode 100644 index 000000000..acf0b5761 --- /dev/null +++ b/tests/xilinx_ug901/black_box_1.ys @@ -0,0 +1,15 @@ +read_verilog black_box_1.v +hierarchy -top black_box_1 +proc +tribuf +flatten +synth +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd black_box_1 # Constrain all select calls below inside the top module +#Vivado synthesizes 1 black box. +#stat +#select -assert-count 0 t:LUT1 +#select -assert-count 1 t:$_TBUF_ +#select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.v b/tests/xilinx_ug901/bytewrite_ram_1b.v new file mode 100644 index 000000000..46d86c297 --- /dev/null +++ b/tests/xilinx_ug901/bytewrite_ram_1b.v @@ -0,0 +1,42 @@ +// Single-Port BRAM with Byte-wide Write Enable +// Read-First mode +// Single-process description +// Compact description of the write with a generate-for +// statement +// Column width and number of columns easily configurable +// +// bytewrite_ram_1b.v +// + +module bytewrite_ram_1b (clk, we, addr, di, do); + +parameter SIZE = 1024; +parameter ADDR_WIDTH = 10; +parameter COL_WIDTH = 8; +parameter NB_COL = 4; + +input clk; +input [NB_COL-1:0] we; +input [ADDR_WIDTH-1:0] addr; +input [NB_COL*COL_WIDTH-1:0] di; +output reg [NB_COL*COL_WIDTH-1:0] do; + +reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0]; + +always @(posedge clk) +begin + do <= RAM[addr]; +end + +generate genvar i; +for (i = 0; i < NB_COL; i = i+1) +begin +always @(posedge clk) +begin + if (we[i]) + RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH]; + end +end +endgenerate + +endmodule diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.ys b/tests/xilinx_ug901/bytewrite_ram_1b.ys new file mode 100644 index 000000000..4f0967801 --- /dev/null +++ b/tests/xilinx_ug901/bytewrite_ram_1b.ys @@ -0,0 +1,22 @@ +read_verilog bytewrite_ram_1b.v +hierarchy -top bytewrite_ram_1b +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd bytewrite_ram_1b +stat +#Vivado synthesizes 1 RAMB36E1. +select -assert-count 1 t:BUFG +select -assert-count 32 t:LUT2 +select -assert-count 8 t:RAMB36E1 + +select -assert-none t:BUFG t:LUT2 t:RAMB36E1 %% t:* %D diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v new file mode 100644 index 000000000..1093b0838 --- /dev/null +++ b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v @@ -0,0 +1,78 @@ +// +// True-Dual-Port BRAM with Byte-wide Write Enable +// No-Change mode +// +// bytewrite_tdp_ram_nc.v +// +// ByteWide Write Enable, - NO_CHANGE mode template - Vivado recomended +module bytewrite_tdp_ram_nc + #( + //--------------------------------------------------------------- + parameter NUM_COL = 4, + parameter COL_WIDTH = 8, + parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth + parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits + //--------------------------------------------------------------- + ) ( + input clkA, + input enaA, + input [NUM_COL-1:0] weA, + input [ADDR_WIDTH-1:0] addrA, + input [DATA_WIDTH-1:0] dinA, + output reg [DATA_WIDTH-1:0] doutA, + + input clkB, + input enaB, + input [NUM_COL-1:0] weB, + input [ADDR_WIDTH-1:0] addrB, + input [DATA_WIDTH-1:0] dinB, + output reg [DATA_WIDTH-1:0] doutB + ); + + + // Core Memory + reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0]; + + // Port-A Operation + generate + genvar i; + for(i=0;i run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/xilinx_ug901/sfir_shifter.v b/tests/xilinx_ug901/sfir_shifter.v new file mode 100644 index 000000000..a8b144bcd --- /dev/null +++ b/tests/xilinx_ug901/sfir_shifter.v @@ -0,0 +1,19 @@ +//sfir_shifter.v +(* dont_touch = "yes" *) +module sfir_shifter #(parameter dsize = 16, nbtap = 4) + (input clk,input [dsize-1:0] datain, output [dsize-1:0] dataout); + + (* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1]; + integer i; + + always @(posedge clk) + begin + tmp[0] <= datain; + for (i=0; i<=2*nbtap-2; i=i+1) + tmp[i+1] <= tmp[i]; + end + + assign dataout = tmp[2*nbtap-1]; + +endmodule +// sfir_shifter diff --git a/tests/xilinx_ug901/sfir_shifter.ys b/tests/xilinx_ug901/sfir_shifter.ys new file mode 100644 index 000000000..b9fbeb8cb --- /dev/null +++ b/tests/xilinx_ug901/sfir_shifter.ys @@ -0,0 +1,16 @@ +read_verilog sfir_shifter.v +hierarchy -top sfir_shifter +proc +flatten +#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +cd sfir_shifter +#Vivado synthesizes 32 FDRE, 16 SRL16E. +stat +select -assert-count 1 t:BUFG +select -assert-count 16 t:SRL16E + +select -assert-none t:BUFG t:SRL16E %% t:* %D diff --git a/tests/xilinx_ug901/shift_registers_0.v b/tests/xilinx_ug901/shift_registers_0.v new file mode 100644 index 000000000..77a3ec893 --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_0.v @@ -0,0 +1,22 @@ +// 8-bit Shift Register +// Rising edge clock +// Active high clock enable +// Concatenation-based template +// File: shift_registers_0.v + +module shift_registers_0 (clk, clken, SI, SO); +parameter WIDTH = 32; +input clk, clken, SI; +output SO; + +reg [WIDTH-1:0] shreg; + +always @(posedge clk) + begin + if (clken) + shreg = {shreg[WIDTH-2:0], SI}; + end + +assign SO = shreg[WIDTH-1]; + +endmodule diff --git a/tests/xilinx_ug901/shift_registers_0.ys b/tests/xilinx_ug901/shift_registers_0.ys new file mode 100644 index 000000000..ae7d23a7f --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_0.ys @@ -0,0 +1,13 @@ +read_verilog shift_registers_0.v +hierarchy -top shift_registers_0 +proc +flatten +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd shift_registers_0 # Constrain all select calls below inside the top module +#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E. +select -assert-count 1 t:BUFG +select -assert-count 1 t:SRLC32E +select -assert-none t:BUFG t:SRLC32E %% t:* %D diff --git a/tests/xilinx_ug901/shift_registers_1.v b/tests/xilinx_ug901/shift_registers_1.v new file mode 100644 index 000000000..d50820e7b --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_1.v @@ -0,0 +1,24 @@ +// 32-bit Shift Register +// Rising edge clock +// Active high clock enable +// For-loop based template +// File: shift_registers_1.v + +module shift_registers_1 (clk, clken, SI, SO); +parameter WIDTH = 32; +input clk, clken, SI; +output SO; +reg [WIDTH-1:0] shreg; + +integer i; +always @(posedge clk) +begin + if (clken) + begin + for (i = 0; i < WIDTH-1; i = i+1) + shreg[i+1] <= shreg[i]; + shreg[0] <= SI; + end +end +assign SO = shreg[WIDTH-1]; +endmodule diff --git a/tests/xilinx_ug901/shift_registers_1.ys b/tests/xilinx_ug901/shift_registers_1.ys new file mode 100644 index 000000000..fb935c446 --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_1.ys @@ -0,0 +1,14 @@ +read_verilog shift_registers_1.v +hierarchy -top shift_registers_1 +proc +flatten + +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd shift_registers_1 # Constrain all select calls below inside the top module +#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E. +select -assert-count 1 t:BUFG +select -assert-count 1 t:SRLC32E +select -assert-none t:BUFG t:SRLC32E %% t:* %D diff --git a/tests/xilinx_ug901/squarediffmacc.v b/tests/xilinx_ug901/squarediffmacc.v new file mode 100644 index 000000000..6535b24c4 --- /dev/null +++ b/tests/xilinx_ug901/squarediffmacc.v @@ -0,0 +1,52 @@ +// This module performs subtraction of two inputs, squaring on the diff +// and then accumulation +// This can be implemented in 1 DSP Block (Ultrascale architecture) +// File : squarediffmacc.v +module squarediffmacc # ( + //Default parameters were changed because of slow test + //parameter SIZEIN = 16, + //SIZEOUT = 40 + parameter SIZEIN = 8, + SIZEOUT = 20 + ) + ( + input clk, + input ce, + input sload, + input signed [SIZEIN-1:0] a, + input signed [SIZEIN-1:0] b, + output signed [SIZEOUT+1:0] accum_out + ); + +// Declare registers for intermediate values +reg signed [SIZEIN-1:0] a_reg, b_reg; +reg signed [SIZEIN:0] diff_reg; +reg sload_reg; +reg signed [2*SIZEIN+1:0] m_reg; +reg signed [SIZEOUT-1:0] adder_out, old_result; + + always @(sload_reg or adder_out) + if (sload_reg) + old_result <= 0; + else + // 'sload' is now and opens the accumulation loop. + // The accumulator takes the next multiplier output + // in the same cycle. + old_result <= adder_out; + + always @(posedge clk) + if (ce) + begin + a_reg <= a; + b_reg <= b; + diff_reg <= a_reg - b_reg; + m_reg <= diff_reg * diff_reg; + sload_reg <= sload; + // Store accumulation result into a register + adder_out <= old_result + m_reg; + end + + // Output accumulation result + assign accum_out = adder_out; + +endmodule // squarediffmacc diff --git a/tests/xilinx_ug901/squarediffmacc.ys b/tests/xilinx_ug901/squarediffmacc.ys new file mode 100644 index 000000000..92474bea3 --- /dev/null +++ b/tests/xilinx_ug901/squarediffmacc.ys @@ -0,0 +1,23 @@ +read_verilog squarediffmacc.v +hierarchy -top squarediffmacc +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +cd squarediffmacc +#Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT. +stat +select -assert-count 1 t:BUFG +select -assert-count 64 t:FDRE +select -assert-count 78 t:LUT2 +select -assert-count 7 t:LUT3 +select -assert-count 11 t:LUT4 +select -assert-count 8 t:LUT5 +select -assert-count 125 t:LUT6 +select -assert-count 44 t:MUXCY +select -assert-count 50 t:MUXF7 +select -assert-count 17 t:MUXF8 +select -assert-count 47 t:XORCY + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx_ug901/squarediffmult.v b/tests/xilinx_ug901/squarediffmult.v new file mode 100644 index 000000000..0f41b67bc --- /dev/null +++ b/tests/xilinx_ug901/squarediffmult.v @@ -0,0 +1,42 @@ +// Squarer support for DSP block (DSP48E2) with +// pre-adder configured +// as subtractor +// File: squarediffmult.v + +module squarediffmult # (parameter SIZEIN = 16) + ( + input clk, ce, rst, + input signed [SIZEIN-1:0] a, b, + output signed [2*SIZEIN+1:0] square_out + ); + + // Declare registers for intermediate values +reg signed [SIZEIN-1:0] a_reg, b_reg; +reg signed [SIZEIN:0] diff_reg; +reg signed [2*SIZEIN+1:0] m_reg, p_reg; + +always @(posedge clk) +begin + if (rst) + begin + a_reg <= 0; + b_reg <= 0; + diff_reg <= 0; + m_reg <= 0; + p_reg <= 0; + end + else + if (ce) + begin + a_reg <= a; + b_reg <= b; + diff_reg <= a_reg - b_reg; + m_reg <= diff_reg * diff_reg; + p_reg <= m_reg; + end +end + +// Output result +assign square_out = p_reg; + +endmodule // squarediffmult diff --git a/tests/xilinx_ug901/squarediffmult.ys b/tests/xilinx_ug901/squarediffmult.ys new file mode 100644 index 000000000..3468e5bb4 --- /dev/null +++ b/tests/xilinx_ug901/squarediffmult.ys @@ -0,0 +1,30 @@ +read_verilog squarediffmult.v +hierarchy -top squarediffmult +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd squarediffmult +stat +#Vivado synthesizes 16 FDRE, 1 DSP48E1. +select -assert-count 1 t:BUFG +select -assert-count 117 t:FDRE +select -assert-count 223 t:LUT2 +select -assert-count 50 t:LUT3 +select -assert-count 38 t:LUT4 +select -assert-count 56 t:LUT5 +select -assert-count 372 t:LUT6 +select -assert-count 49 t:MUXCY +select -assert-count 99 t:MUXF7 +select -assert-count 26 t:MUXF8 +select -assert-count 51 t:XORCY + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx_ug901/top_mux.v b/tests/xilinx_ug901/top_mux.v new file mode 100644 index 000000000..c23c7491c --- /dev/null +++ b/tests/xilinx_ug901/top_mux.v @@ -0,0 +1,18 @@ +// Multiplexer using case statement +module mux4 (sel, a, b, c, d, outmux); +input [1:0] sel; +input [1:0] a, b, c, d; +output [1:0] outmux; +reg [1:0] outmux; + +always @ * + begin + case(sel) + 2'b00 : outmux = a; + 2'b01 : outmux = b; + 2'b10 : outmux = c; + 2'b11 : outmux = d; + endcase + end +endmodule + diff --git a/tests/xilinx_ug901/top_mux.ys b/tests/xilinx_ug901/top_mux.ys new file mode 100644 index 000000000..0245f3bbc --- /dev/null +++ b/tests/xilinx_ug901/top_mux.ys @@ -0,0 +1,13 @@ +read_verilog top_mux.v +hierarchy -top mux4 +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +cd mux4 +#Vivado synthesizes 2 LUT. +stat +select -assert-count 2 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D diff --git a/tests/xilinx_ug901/tristates_1.v b/tests/xilinx_ug901/tristates_1.v new file mode 100644 index 000000000..0038a9989 --- /dev/null +++ b/tests/xilinx_ug901/tristates_1.v @@ -0,0 +1,17 @@ +// Tristate Description Using Combinatorial Always Block +// File: tristates_1.v +// +module tristates_1 (T, I, O); +input T, I; +output O; +reg O; + +always @(T or I) +begin + if (~T) + O = I; + else + O = 1'bZ; +end + +endmodule diff --git a/tests/xilinx_ug901/tristates_1.ys b/tests/xilinx_ug901/tristates_1.ys new file mode 100644 index 000000000..7c13dc227 --- /dev/null +++ b/tests/xilinx_ug901/tristates_1.ys @@ -0,0 +1,13 @@ +read_verilog tristates_1.v +hierarchy -top tristates_1 +proc +tribuf +flatten +synth +equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristates_1 # Constrain all select calls below inside the top module +#Vivado synthesizes 3 IBUF, 1 OBUFT. +select -assert-count 1 t:LUT1 +select -assert-count 1 t:$_TBUF_ +select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/tristates_2.v b/tests/xilinx_ug901/tristates_2.v new file mode 100644 index 000000000..0c70a1257 --- /dev/null +++ b/tests/xilinx_ug901/tristates_2.v @@ -0,0 +1,10 @@ +// Tristate Description Using Concurrent Assignment +// File: tristates_2.v +// +module tristates_2 (T, I, O); +input T, I; +output O; + +assign O = (~T) ? I: 1'bZ; + +endmodule diff --git a/tests/xilinx_ug901/tristates_2.ys b/tests/xilinx_ug901/tristates_2.ys new file mode 100644 index 000000000..ba2e1d855 --- /dev/null +++ b/tests/xilinx_ug901/tristates_2.ys @@ -0,0 +1,13 @@ +read_verilog tristates_2.v +hierarchy -top tristates_2 +proc +tribuf +flatten +synth +equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristates_2 # Constrain all select calls below inside the top module +#Vivado synthesizes 3 IBUF, 1 OBUFT. +select -assert-count 1 t:LUT1 +select -assert-count 1 t:$_TBUF_ +select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v new file mode 100644 index 000000000..f5e843dc9 --- /dev/null +++ b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v @@ -0,0 +1,78 @@ +// Xilinx UltraRAM Single Port No Change Mode. This code implements +// a parameterizable UltraRAM block in No Change mode. The behavior of this RAM is +// when data is written, the output of RAM is unchanged. Only when write is +// inactive data corresponding to the address is presented on the output port. +// +module xilinx_ultraram_single_port_no_change #( +//Default parameters were changed because of slow test + //parameter AWIDTH = 12, // Address Width + //parameter DWIDTH = 72, // Data Width + //parameter NBPIPE = 3 // Number of pipeline Registers + parameter AWIDTH = 8, // Address Width + parameter DWIDTH = 8, // Data Width + parameter NBPIPE = 3 // Number of pipeline Registers + ) ( + input clk, // Clock + input rst, // Reset + input we, // Write Enable + input regce, // Output Register Enable + input mem_en, // Memory Enable + input [DWIDTH-1:0] din, // Data Input + input [AWIDTH-1:0] addr, // Address Input + output reg [DWIDTH-1:0] dout // Data Output + ); + +(* ram_style = "ultra" *) +reg [DWIDTH-1:0] mem[(1<