From 2aefa5e19fc09b95affa7e61d162a6b95bfacd92 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Mon, 9 Jan 2017 16:43:24 -0800 Subject: [PATCH] intel/fs: Fix FB read header setup for SIMD32. Reviewed-by: Jason Ekstrand Reviewed-by: Matt Turner --- src/intel/compiler/brw_fs.cpp | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index a63581b1ee5..07be2e3da42 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -4187,12 +4187,21 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, static void lower_fb_read_logical_send(const fs_builder &bld, fs_inst *inst) { - const fs_builder &ubld = bld.exec_all(); + const fs_builder &ubld = bld.exec_all().group(8, 0); const unsigned length = 2; - const fs_reg header = ubld.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD, length); + const fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD, length); - ubld.group(16, 0) - .MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + if (bld.group() < 16) { + ubld.group(16, 0).MOV(header, retype(brw_vec8_grf(0, 0), + BRW_REGISTER_TYPE_UD)); + } else { + assert(bld.group() < 32); + const fs_reg header_sources[] = { + retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD), + retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD) + }; + ubld.LOAD_PAYLOAD(header, header_sources, ARRAY_SIZE(header_sources), 0); + } inst->resize_sources(1); inst->src[0] = header; -- 2.30.2