From 2b3a5b0e96f6a45fb37cf3549f3571cc23377324 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 8 Mar 2022 15:46:15 +0000 Subject: [PATCH] remove ld_stbs_done from dcache: not needed --- src/soc/experiment/dcache.py | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 9e75cc01..917e9818 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1589,20 +1589,14 @@ class DCache(Elaboratable, DCacheConfig): pass with m.Case(State.RELOAD_WAIT_ACK): - ld_stbs_done = Signal() - # Requests are all sent if stb is 0 - comb += ld_stbs_done.eq(~r1.wb.stb) # If we are still sending requests, was one accepted? with m.If((~bus.stall) & r1.wb.stb): - # That was the last word? We are done sending. - # Clear stb and set ld_stbs_done so we can handle an - # eventual last ack on the same cycle. + # That was the last word? We are done sending. Clear stb # sigh - reconstruct wb adr with 3 extra 0s at front wb_adr = Cat(Const(0, self.ROW_OFF_BITS), r1.wb.adr) with m.If(self.is_last_row_addr(wb_adr, r1.end_row_ix)): sync += r1.wb.stb.eq(0) - comb += ld_stbs_done.eq(1) # Calculate the next row address in the current cache line rlen = self.LINE_OFF_BITS-self.ROW_OFF_BITS @@ -1641,7 +1635,7 @@ class DCache(Elaboratable, DCacheConfig): sync += r1.use_forward1.eq(1) # Check for completion - with m.If(ld_stbs_done & lastrow): + with m.If(lastrow): # Complete wishbone cycle sync += r1.wb.cyc.eq(0) -- 2.30.2