From 2b404a650493514896b345e70713c1c3bbe58a26 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 17 Dec 2013 03:11:30 +0100 Subject: [PATCH] radeonsi: improve HiZ precision for less and lequal depth functions MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit r600g needs this too. Reviewed-by: Michel Dänzer --- src/gallium/drivers/radeonsi/si_state.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 8e0880419bc..c1107c66001 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -1815,7 +1815,13 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, /* use htile only for first level */ if (rtex->htile_buffer && !level) { z_info |= S_028040_TILE_SURFACE_ENABLE(1); - /* Force off means no force, DB_SHADER_CONTROL decides */ + + /* This is optimal for the clear value of 1.0 and using + * the LESS and LEQUAL test functions. Set this to 0 + * for the opposite case. This can only be changed when + * clearing. */ + z_info |= S_028040_ZRANGE_PRECISION(1); + uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b); db_htile_data_base = va >> 8; db_htile_surface = S_028ABC_FULL_CACHE(1); -- 2.30.2