From 2b6da534d53396208ddb6b40fb8c13f4ad7d4058 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 20 Feb 2022 23:51:32 +0000 Subject: [PATCH] same as shiftrot, split out separate pipelines for logical stages in order to meet FPGA timing --- src/soc/fu/logical/pipeline.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/logical/pipeline.py b/src/soc/fu/logical/pipeline.py index a16bd78a..a0f00d1d 100644 --- a/src/soc/fu/logical/pipeline.py +++ b/src/soc/fu/logical/pipeline.py @@ -8,11 +8,15 @@ from soc.fu.logical.output_stage import LogicalOutputStage class LogicalStages1(PipeModBaseChain): def get_chain(self): inp = LogicalInputStage(self.pspec) + return [inp] + +class LogicalStages2(PipeModBaseChain): + def get_chain(self): main = LogicalMainStage(self.pspec) - return [inp, main] + return [main] -class LogicalStages2(PipeModBaseChain): +class LogicalStages3(PipeModBaseChain): def get_chain(self): out = LogicalOutputStage(self.pspec) return [out] @@ -24,11 +28,13 @@ class LogicalBasePipe(ControlBase): self.pspec = pspec self.pipe1 = LogicalStages1(pspec) self.pipe2 = LogicalStages2(pspec) - self._eqs = self.connect([self.pipe1, self.pipe2]) + self.pipe3 = LogicalStages3(pspec) + self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3]) def elaborate(self, platform): m = ControlBase.elaborate(self, platform) m.submodules.logical_pipe1 = self.pipe1 m.submodules.logical_pipe2 = self.pipe2 + m.submodules.logical_pipe3 = self.pipe3 m.d.comb += self._eqs return m -- 2.30.2