From 2b7810e16ccb87b942f53dc57679f39bd94587d5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 19 Oct 2023 10:45:27 +0100 Subject: [PATCH] add fixedloadshift.mdwn which is a copy of fixedload.mdwn not edited for descriptions or pseudocode yet. https://bugs.libre-soc.org/show_bug.cgi?id=1090 --- openpower/isa/fixedloadshift.mdwn | 280 ++++++++++++++++++++++++++++++ 1 file changed, 280 insertions(+) create mode 100644 openpower/isa/fixedloadshift.mdwn diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn new file mode 100644 index 00000000..75be291a --- /dev/null +++ b/openpower/isa/fixedloadshift.mdwn @@ -0,0 +1,280 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# Load Byte and Zero Indexed + +X-Form + +* lbzx RT,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + RT <- ([0] * (XLEN-8)) || MEM(EA, 1) + +Special Registers Altered: + + None + +# Load Byte and Zero with Update Indexed + +X-Form + +* lbzux RT,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + RT <- ([0] * (XLEN-8)) || MEM(EA, 1) + RA <- EA + +Special Registers Altered: + + None + +# Load Halfword and Zero Indexed + +X-Form + +* lhzx RT,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + RT <- ([0] * (XLEN-16)) || MEM(EA, 2) + +Special Registers Altered: + + None + +# Load Halfword and Zero with Update Indexed + +X-Form + +* lhzux RT,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + RT <- ([0] * (XLEN-16)) || MEM(EA, 2) + RA <- EA + +Special Registers Altered: + + None + +# Load Halfword Algebraic Indexed + +X-Form + +* lhax RT,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + RT <- EXTS(MEM(EA, 2)) + +Special Registers Altered: + + None + +# Load Halfword Algebraic with Update Indexed + +X-Form + +* lhaux RT,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + RT <- EXTS(MEM(EA, 2)) + RA <- EA + +Special Registers Altered: + + None + +# Load Word and Zero Indexed + +X-Form + +* lwzx RT,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + RT <- [0] * 32 || MEM(EA, 4) + +Special Registers Altered: + + None + +# Load Word and Zero with Update Indexed + +X-Form + +* lwzux RT,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + RT <- [0] * 32 || MEM(EA, 4) + RA <- EA + +Special Registers Altered: + + None + +# Load Word Algebraic Indexed + +X-Form + +* lwax RT,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + RT <- EXTS(MEM(EA, 4)) + +Special Registers Altered: + + None + +# Load Word Algebraic with Update Indexed + +X-Form + +* lwaux RT,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + RT <- EXTS(MEM(EA, 4)) + RA <- EA + +Special Registers Altered: + + None + +# Load Doubleword Indexed + +X-Form + +* ldx RT,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + RT <- MEM(EA, 8) + +Special Registers Altered: + + None + +# Load Doubleword with Update Indexed + +X-Form + +* ldux RT,RA,RB + +Pseudo-code: + + EA <- (RA) + (RB) + RT <- MEM(EA, 8) + RA <- EA + +Special Registers Altered: + + None + + + +# Load Halfword Byte-Reverse Indexed + +X-Form + +* lhbrx RT,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + load_data <- MEM(EA, 2) + RT <- [0]*48 || load_data[8:15] || load_data[0:7] + +Special Registers Altered: + + None + +# Load Word Byte-Reverse Indexed + +X-Form + +* lwbrx RT,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + load_data <- MEM(EA, 4) + RT <- ([0] * 32 || load_data[24:31] || load_data[16:23] + || load_data[8:15] || load_data[0:7]) + +Special Registers Altered: + + None + + + + +# Load Doubleword Byte-Reverse Indexed + +X-Form + +* ldbrx RT,RA,RB + +Pseudo-code: + + b <- (RA|0) + EA <- b + (RB) + load_data <- MEM(EA, 8) + RT <- (load_data[56:63] || load_data[48:55] + || load_data[40:47] || load_data[32:39] + || load_data[24:31] || load_data[16:23] + || load_data[8:15] || load_data[0:7]) + +Special Registers Altered: + + None + -- 2.30.2