From 2b7dcaba26f793e49acf82fa8408568b810369eb Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Mon, 3 Feb 2020 14:41:36 -0500 Subject: [PATCH] Move experiments with partition methods to a separate folder --- .../part_cmp/{ => experiments}/eq_combiner.py | 0 .../part_cmp/experiments/formal/.gitignore | 1 + .../{ => experiments}/formal/proof_eq.py | 2 +- src/ieee754/part_cmp/experiments/test.py | 86 +++++++++++++++++++ 4 files changed, 88 insertions(+), 1 deletion(-) rename src/ieee754/part_cmp/{ => experiments}/eq_combiner.py (100%) create mode 100644 src/ieee754/part_cmp/experiments/formal/.gitignore rename src/ieee754/part_cmp/{ => experiments}/formal/proof_eq.py (97%) create mode 100644 src/ieee754/part_cmp/experiments/test.py diff --git a/src/ieee754/part_cmp/eq_combiner.py b/src/ieee754/part_cmp/experiments/eq_combiner.py similarity index 100% rename from src/ieee754/part_cmp/eq_combiner.py rename to src/ieee754/part_cmp/experiments/eq_combiner.py diff --git a/src/ieee754/part_cmp/experiments/formal/.gitignore b/src/ieee754/part_cmp/experiments/formal/.gitignore new file mode 100644 index 00000000..37ad79e3 --- /dev/null +++ b/src/ieee754/part_cmp/experiments/formal/.gitignore @@ -0,0 +1 @@ +proof_*/** diff --git a/src/ieee754/part_cmp/formal/proof_eq.py b/src/ieee754/part_cmp/experiments/formal/proof_eq.py similarity index 97% rename from src/ieee754/part_cmp/formal/proof_eq.py rename to src/ieee754/part_cmp/experiments/formal/proof_eq.py index b72bad6d..80fd7f1d 100644 --- a/src/ieee754/part_cmp/formal/proof_eq.py +++ b/src/ieee754/part_cmp/experiments/formal/proof_eq.py @@ -6,7 +6,7 @@ from nmigen.asserts import Assert, AnyConst from nmigen.test.utils import FHDLTestCase from nmigen.cli import rtlil -from ieee754.part_cmp.eq_combiner import EQCombiner +from ieee754.part_cmp.experiments.eq_combiner import EQCombiner import unittest diff --git a/src/ieee754/part_cmp/experiments/test.py b/src/ieee754/part_cmp/experiments/test.py new file mode 100644 index 00000000..18a24566 --- /dev/null +++ b/src/ieee754/part_cmp/experiments/test.py @@ -0,0 +1,86 @@ +from ieee754.part_mul_add.partpoints import PartitionPoints +import ieee754.part_cmp.equal_ortree as ortree +import ieee754.part_cmp.equal as equal +from nmigen.cli import rtlil +from nmigen import Signal, Module + +def create_ilang(mod, name, ports): + vl = rtlil.convert(mod, ports=ports) + with open(name, "w") as f: + f.write(vl) + +def create_ortree(width, points): + sig = Signal(len(points.values())) + for i, key in enumerate(points): + points[key] = sig[i] + eq = ortree.PartitionedEq(width, points) + + create_ilang(eq, "ortree.il", [eq.a, eq.b, eq.output, sig]) + +def create_equal(width, points): + sig = Signal(len(points.values())) + for i, key in enumerate(points): + points[key] = sig[i] + + eq = equal.PartitionedEq(width, points) + + create_ilang(eq, "equal.il", [eq.a, eq.b, eq.output, sig]) + + +if __name__ == "__main__": + points = PartitionPoints() + sig = Signal(7) + for i in range(sig.width): + points[i*8+8] = True + + # create_equal(32, points) + create_ortree(64, points) + + + + + +# ortree: +# === design hierarchy === + + # top 1 + # mux1 1 + # mux2 1 + # mux3 1 + + # Number of wires: 49 + # Number of wire bits: 89 + # Number of public wires: 36 + # Number of public wire bits: 76 + # Number of memories: 0 + # Number of memory bits: 0 + # Number of processes: 0 + # Number of cells: 29 + # $_MUX_ 6 + # $_NOR_ 1 + # $_NOT_ 3 + # $_OR_ 8 + # $_XOR_ 11 + + +# equals: +# === top === + +# Number of wires: 121 +# Number of wire bits: 161 +# Number of public wires: 12 +# Number of public wire bits: 52 +# Number of memories: 0 +# Number of memory bits: 0 +# Number of processes: 0 +# Number of cells: 113 +# $_ANDNOT_ 32 +# $_AND_ 7 +# $_MUX_ 4 +# $_NAND_ 1 +# $_NOR_ 2 +# $_NOT_ 1 +# $_ORNOT_ 6 +# $_OR_ 44 +# $_XNOR_ 1 +# $_XOR_ 15 -- 2.30.2