From 2b8032ccc332af27614b4e90db20f8f6c64ec361 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 30 Jul 2020 13:27:55 +0100
Subject: [PATCH] ha! have to explicitly specify the ports when writing out to
 ilang or verilog this gives unused signals that default to a non-zero value
 to inherently set by default to that value. exposing them externally via
 ports makes setting them the *users*

---
 src/soc/experiment/l0_cache.py   |  5 ++++-
 src/soc/simple/issuer.py         | 19 ++++++++++++++++++-
 src/soc/simple/issuer_verilog.py |  2 +-
 3 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 7ffaa05d..cc74c538 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -259,10 +259,13 @@ class L0CacheBuffer(Elaboratable):
 
         return m
 
-    def ports(self):
+    def __iter__(self):
         for p in self.dports:
             yield from p.ports()
 
+    def ports(self):
+        return list(self)
+
 
 class TstL0CacheBuffer(Elaboratable):
     def __init__(self, pspec, n_units=3):
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 1c3574fa..c45bb28a 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -211,6 +211,23 @@ class TestIssuer(Elaboratable):
     def ports(self):
         return list(self)
 
+    def external_ports(self):
+        return self.pc_i.ports() + [self.pc_o,
+                                    self.go_insn_i,
+                                    self.memerr_o,
+                                    self.core_start_i,
+                                    self.core_stop_i,
+                                    self.core_bigendian_i,
+                                    self.busy_o,
+                                    self.halted_o,
+                                    ] + \
+                self.imem.ports() + \
+                self.core.l0.cmpi.lsmem.lsi.ports()
+
+
+    def ports(self):
+        return list(self)
+
 
 if __name__ == '__main__':
     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
@@ -227,6 +244,6 @@ if __name__ == '__main__':
     vl = main(dut, ports=dut.ports(), name="test_issuer")
 
     if len(sys.argv) == 1:
-        vl = rtlil.convert(dut, ports=dut.ports(), name="test_issuer")
+        vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
         with open("test_issuer.il", "w") as f:
             f.write(vl)
diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 14a8d53d..d77464b5 100644
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -24,6 +24,6 @@ if __name__ == '__main__':
                          units=units)
     dut = TestIssuer(pspec)
 
-    vl = verilog.convert(dut, ports=dut.ports(), name="test_issuer")
+    vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
     with open(sys.argv[1], "w") as f:
         f.write(vl)
-- 
2.30.2