From 2b8b62c55bb26e887a86d42ef645daa0ed0007ee Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 17 Jun 2020 15:25:28 -0400 Subject: [PATCH] ac/nir: fix 64-bit division for GL CTS This fixes: KHR-GL45.gpu_shader_fp64.builtin.mod_* Fixes: ba2ec1f3 "ac/nir: use llvm.amdgcn.rcp in ac_build_fdiv()" Acked-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/llvm/ac_llvm_build.c | 5 +++++ src/amd/llvm/ac_nir_to_llvm.c | 11 +++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/amd/llvm/ac_llvm_build.c b/src/amd/llvm/ac_llvm_build.c index 77681834ffa..6d5d1f7bab2 100644 --- a/src/amd/llvm/ac_llvm_build.c +++ b/src/amd/llvm/ac_llvm_build.c @@ -705,6 +705,11 @@ ac_build_fdiv(struct ac_llvm_context *ctx, unsigned type_size = ac_get_type_size(LLVMTypeOf(den)); const char *name; + /* For doubles, we need precise division to pass GLCTS. */ + if (ctx->float_mode == AC_FLOAT_MODE_DEFAULT_OPENGL && + type_size == 8) + return LLVMBuildFDiv(ctx->builder, num, den, ""); + if (type_size == 2) name = "llvm.amdgcn.rcp.f16"; else if (type_size == 4) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index b90a7e3dcf2..bd3cc246e5c 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -704,8 +704,15 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], ""); break; case nir_op_frcp: - result = emit_intrin_1f_param(&ctx->ac, "llvm.amdgcn.rcp", - ac_to_float_type(&ctx->ac, def_type), src[0]); + /* For doubles, we need precise division to pass GLCTS. */ + if (ctx->ac.float_mode == AC_FLOAT_MODE_DEFAULT_OPENGL && + ac_get_type_size(def_type) == 8) { + result = LLVMBuildFDiv(ctx->ac.builder, ctx->ac.f64_1, + ac_to_float(&ctx->ac, src[0]), ""); + } else { + result = emit_intrin_1f_param(&ctx->ac, "llvm.amdgcn.rcp", + ac_to_float_type(&ctx->ac, def_type), src[0]); + } break; case nir_op_iand: result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], ""); -- 2.30.2