From 2b8dc52c131a6d21b3562f18c80673aaab551ad1 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 9 Mar 2013 19:03:13 +0100 Subject: [PATCH] Use common definition for FinalizeError --- migen/bus/asmibus.py | 3 --- migen/fhdl/structure.py | 3 +++ migen/pytholite/reg.py | 3 --- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/migen/bus/asmibus.py b/migen/bus/asmibus.py index cab327a7..6f639e95 100644 --- a/migen/bus/asmibus.py +++ b/migen/bus/asmibus.py @@ -3,9 +3,6 @@ from migen.genlib.misc import optree from migen.bus.transactions import * from migen.sim.generic import Proxy, PureSimulable -class FinalizeError(Exception): - pass - (SLOT_EMPTY, SLOT_PENDING, SLOT_PROCESSING) = range(3) class Slot: diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py index 8052fdff..3b5ca53e 100644 --- a/migen/fhdl/structure.py +++ b/migen/fhdl/structure.py @@ -276,3 +276,6 @@ class ClockDomain: n_rst = n2 self.clk = Signal(name_override=n_clk) self.rst = Signal(name_override=n_rst) + +class FinalizeError(Exception): + pass diff --git a/migen/pytholite/reg.py b/migen/pytholite/reg.py index 5ec49c4a..6346753d 100644 --- a/migen/pytholite/reg.py +++ b/migen/pytholite/reg.py @@ -3,9 +3,6 @@ from operator import itemgetter from migen.fhdl.structure import * from migen.fhdl import visit as fhdl -class FinalizeError(Exception): - pass - class AbstractLoad: def __init__(self, target, source): self.target = target -- 2.30.2