From 2b9397ff5bec4dd48e13ea104826c00e792d7d34 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 6 Mar 2015 07:51:44 +0100 Subject: [PATCH] targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True) --- misoclib/soc/sdram.py | 5 ++-- targets/de0nano.py | 43 +++++++++++++++++---------------- targets/kc705.py | 39 +++++++++++++++--------------- targets/mlabs_video.py | 55 +++++++++++++++++++++++------------------- targets/pipistrello.py | 53 ++++++++++++++++++++-------------------- targets/ppro.py | 37 ++++++++++++++-------------- 6 files changed, 121 insertions(+), 111 deletions(-) diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index 4acc4297..df4322eb 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -70,6 +70,7 @@ class SDRAMSoC(SoC): raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width)) def do_finalize(self): - if not self._sdram_phy_registered: - raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()") + if not self.with_sdram: + if not self._sdram_phy_registered: + raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()") SoC.do_finalize(self) diff --git a/targets/de0nano.py b/targets/de0nano.py index ee4faa5a..82ae5bd9 100644 --- a/targets/de0nano.py +++ b/targets/de0nano.py @@ -87,28 +87,29 @@ class BaseSoC(SDRAMSoC): with_rom=True, **kwargs) - sdram_geom = sdram.GeomSettings( - bank_a=2, - row_a=13, - col_a=9 - ) - - sdram_timing = sdram.TimingSettings( - tRP=self.ns(20), - tRCD=self.ns(20), - tWR=self.ns(20), - tWTR=2, - tREFI=self.ns(7800, False), - tRFC=self.ns(70), - - req_queue_size=8, - read_time=32, - write_time=16 - ) - self.submodules.crg = _CRG(platform) - self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) - self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing) + if not self.with_sdram: + sdram_geom = sdram.GeomSettings( + bank_a=2, + row_a=13, + col_a=9 + ) + + sdram_timing = sdram.TimingSettings( + tRP=self.ns(20), + tRCD=self.ns(20), + tWR=self.ns(20), + tWTR=2, + tREFI=self.ns(7800, False), + tRFC=self.ns(70), + + req_queue_size=8, + read_time=32, + write_time=16 + ) + + self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) + self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing) default_subtarget = BaseSoC diff --git a/targets/kc705.py b/targets/kc705.py index ff3a8232..0281691c 100644 --- a/targets/kc705.py +++ b/targets/kc705.py @@ -80,25 +80,26 @@ class BaseSoC(SDRAMSoC): self.submodules.crg = _CRG(platform) - sdram_geom = sdram.GeomSettings( - bank_a=3, - row_a=16, - col_a=10 - ) - sdram_timing = sdram.TimingSettings( - tRP=self.ns(15), - tRCD=self.ns(15), - tWR=self.ns(15), - tWTR=2, - tREFI=self.ns(7800, False), - tRFC=self.ns(70), - - req_queue_size=8, - read_time=32, - write_time=16 - ) - self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3") - self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) + if not self.with_sdram: + sdram_geom = sdram.GeomSettings( + bank_a=3, + row_a=16, + col_a=10 + ) + sdram_timing = sdram.TimingSettings( + tRP=self.ns(15), + tRCD=self.ns(15), + tWR=self.ns(15), + tWTR=2, + tREFI=self.ns(7800, False), + tRFC=self.ns(70), + + req_queue_size=8, + read_time=32, + write_time=16 + ) + self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3") + self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) spiflash_pads = platform.request("spiflash") spiflash_pads.clk = Signal() diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index 498237bd..a281bf8f 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -38,26 +38,35 @@ class BaseSoC(SDRAMSoC): cpu_reset_address=0x00180000, **kwargs) - sdram_geom = sdram.GeomSettings( - bank_a=2, - row_a=13, - col_a=10 - ) - sdram_timing = sdram.TimingSettings( - tRP=self.ns(15), - tRCD=self.ns(15), - tWR=self.ns(15), - tWTR=2, - tREFI=self.ns(7800, False), - tRFC=self.ns(70), - - req_queue_size=8, - read_time=32, - write_time=16 - ) - self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", - rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1") - self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) + self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq) + + if not self.with_sdram: + sdram_geom = sdram.GeomSettings( + bank_a=2, + row_a=13, + col_a=10 + ) + sdram_timing = sdram.TimingSettings( + tRP=self.ns(15), + tRCD=self.ns(15), + tWR=self.ns(15), + tWTR=2, + tREFI=self.ns(7800, False), + tRFC=self.ns(70), + + req_queue_size=8, + read_time=32, + write_time=16 + ) + self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", + rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1") + self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) + + + self.comb += [ + self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), + self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb) + ] self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"), self.ns(110), self.ns(50)) @@ -67,11 +76,7 @@ class BaseSoC(SDRAMSoC): if not self.with_rom: self.register_rom(self.norflash.bus) - self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq) - self.comb += [ - self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), - self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb) - ] + platform.add_platform_command(""" INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2"; INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3"; diff --git a/targets/pipistrello.py b/targets/pipistrello.py index 61b3d172..41c1447b 100644 --- a/targets/pipistrello.py +++ b/targets/pipistrello.py @@ -96,32 +96,33 @@ class BaseSoC(SDRAMSoC): self.submodules.crg = _CRG(platform, clk_freq) - sdram_geom = sdram.GeomSettings( - bank_a=2, - row_a=13, - col_a=10 - ) - sdram_timing = sdram.TimingSettings( - tRP=self.ns(15), - tRCD=self.ns(15), - tWR=self.ns(15), - tWTR=2, - tREFI=self.ns(64*1000*1000/8192, False), - tRFC=self.ns(72), - req_queue_size=8, - read_time=32, - write_time=16 - ) - self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("sdram"), - "LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1") - self.comb += [ - self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), - self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), - ] - platform.add_platform_command(""" -PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; -""") - self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) + if not self.with_sdram: + sdram_geom = sdram.GeomSettings( + bank_a=2, + row_a=13, + col_a=10 + ) + sdram_timing = sdram.TimingSettings( + tRP=self.ns(15), + tRCD=self.ns(15), + tWR=self.ns(15), + tWTR=2, + tREFI=self.ns(64*1000*1000/8192, False), + tRFC=self.ns(72), + req_queue_size=8, + read_time=32, + write_time=16 + ) + self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("sdram"), + "LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1") + self.comb += [ + self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), + self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), + ] + platform.add_platform_command(""" + PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; + """) + self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=11, div=2) self.flash_boot_address = 0x180000 diff --git a/targets/ppro.py b/targets/ppro.py index 1dfad435..347f665a 100644 --- a/targets/ppro.py +++ b/targets/ppro.py @@ -73,24 +73,25 @@ class BaseSoC(SDRAMSoC): self.submodules.crg = _CRG(platform, clk_freq) - sdram_geom = sdram.GeomSettings( - bank_a=2, - row_a=12, - col_a=8 - ) - sdram_timing = sdram.TimingSettings( - tRP=self.ns(15), - tRCD=self.ns(15), - tWR=self.ns(14), - tWTR=2, - tREFI=self.ns(64*1000*1000/4096, False), - tRFC=self.ns(66), - req_queue_size=8, - read_time=32, - write_time=16 - ) - self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) - self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing) + if not self.with_sdram: + sdram_geom = sdram.GeomSettings( + bank_a=2, + row_a=12, + col_a=8 + ) + sdram_timing = sdram.TimingSettings( + tRP=self.ns(15), + tRCD=self.ns(15), + tWR=self.ns(14), + tWTR=2, + tREFI=self.ns(64*1000*1000/4096, False), + tRFC=self.ns(66), + req_queue_size=8, + read_time=32, + write_time=16 + ) + self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) + self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing) self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6) self.flash_boot_address = 0x70000 -- 2.30.2