From 2b9acd3196c5552cf13defc5d9483be6b9387637 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 23 Dec 2021 16:24:56 +0000 Subject: [PATCH] enabled debug printing of MSR --- sim.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sim.py b/sim.py index accac4f..c4d1b9d 100755 --- a/sim.py +++ b/sim.py @@ -304,9 +304,9 @@ class LibreSoCSim(SoCSDRAM): If(dbg_addr == 0b10, # PC pc.eq(dbg_dout), # capture PC ), - #If(dbg_addr == 0b11, # MSR - # Display(" msr: %016x", dbg_dout), - #), + If(dbg_addr == 0b11, # MSR + Display(" msr: %016x", dbg_dout), + ), If(dbg_addr == 0b1000, # CR Display(" cr : %016x", dbg_dout), ), -- 2.30.2