From 2badf0e85b3a54119b08c559dc18aed43a156295 Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Thu, 31 May 2018 16:03:44 -0700 Subject: [PATCH] i965/icl: Don't set float blend optimization bit in CACHE_MODE_SS CACHE_MODE_SS is not listed in gfxspecs table for user mode non-privileged registers. So, making any changes from Mesa will do nothing. Kernel is already setting this bit in CACHE_MODE_SS register which is saved/restored to/from the HW context image. Signed-off-by: Anuj Phogat Reviewed-by: Jason Ekstrand Reviewed-by: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_state_upload.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index d8273aa5734..757426407c3 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -64,10 +64,6 @@ brw_upload_initial_gpu_state(struct brw_context *brw) brw_upload_invariant_state(brw); if (devinfo->gen == 10 || devinfo->gen == 11) { - brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS, - REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) | - GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE); - /* From gen10 workaround table in h/w specs: * * "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1 -- 2.30.2