From 2bb0b7738b02663cef72319f53849a3fcd1507f0 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Tue, 15 Jan 2019 16:06:19 -0500 Subject: [PATCH] back.rtlil: Generate $anyconst and $anyseq cells. --- nmigen/back/rtlil.py | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 8982f23..2f0ed6c 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -370,6 +370,26 @@ class _RHSValueCompiler(_ValueCompiler): value_twos_compl = value.value & ((1 << value.nbits) - 1) return "{}'{:0{}b}".format(value.nbits, value_twos_compl, value.nbits) + def on_AnyConst(self, value): + res_bits, res_sign = value.shape() + res = self.s.rtlil.wire(width=res_bits) + self.s.rtlil.cell("$anyconst", ports={ + "\\Y": res, + }, params={ + "Y_WIDTH": res_bits, + }, src=src(value.src_loc)) + return res + + def on_AnySeq(self, value): + res_bits, res_sign = value.shape() + res = self.s.rtlil.wire(width=res_bits) + self.s.rtlil.cell("$anyseq", ports={ + "\\Y": res, + }, params={ + "Y_WIDTH": res_bits, + }, src=src(value.src_loc)) + return res + def on_Signal(self, value): wire_curr, wire_next = self.s.resolve(value) return wire_curr @@ -503,6 +523,12 @@ class _LHSValueCompiler(_ValueCompiler): def on_Const(self, value): raise TypeError # :nocov: + def on_AnyConst(self, value): + raise TypeError # :nocov: + + def on_AnySeq(self, value): + raise TypeError # :nocov: + def on_Operator(self, value): raise TypeError # :nocov: -- 2.30.2