From 2bb2c8544423adf1366017ef12ef9d71e7014591 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Thu, 28 Apr 2022 20:25:13 +0200 Subject: [PATCH] add paragraph about firmware address --- HDL_workflow/ls2.mdwn | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/HDL_workflow/ls2.mdwn b/HDL_workflow/ls2.mdwn index ec647175a..af04de74a 100644 --- a/HDL_workflow/ls2.mdwn +++ b/HDL_workflow/ls2.mdwn @@ -72,3 +72,21 @@ In fact any core can be used with ls, as long as it is compliant with the interfaces. Both Wishbone Interfaces must be WB4 Pipeline compliant (proper stall handling) or the stall signal faked externally with a wrapper: `stall=stb&~ack` + +# Using ls2 with verilator + +first you need to build hello_world (or any other firmware) to start at +0xff000000. Then you can run build ls.v using that firmware: + + python3 src/ls2.py sim /tmp/ff000000_hw.bin + +The output of that command is: + + platform sim /tmp/ff000000_hw.bin None + fpga sim firmware /tmp/ff000000_hw.bin + ddr pins None + spiflash pins None + ethmac pins None + hyperram pins [] + fw at address ff000000 + SRAM 0x8000 at address 0x0 \ No newline at end of file -- 2.30.2