From 2bdaa48f551195d619a096cb14cf7e3683f4dd48 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 31 Jan 2022 15:47:06 +0000
Subject: [PATCH] add microwatt external core build target to Makefile

---
 Makefile | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Makefile b/Makefile
index 3d4ea62d..20bce282 100644
--- a/Makefile
+++ b/Makefile
@@ -56,6 +56,11 @@ ls180_4k_verilog:
 	        --enable-xics --enable-sram4x4kblock --disable-svp64 \
 			src/soc/litex/florent/libresoc/libresoc.v
 
+# build microwatt "external core"
+microwatt_external_core:
+	python3 simple/issuer_verilog.py --microwatt-compat --enable-mmu \
+            external_core_top.v
+
 # build the litex libresoc SoC without 4k SRAMs
 ls180_verilog_build: ls180_verilog
 	make -C soc/soc/litex/florent ls180
-- 
2.30.2