From 2be4091a007b94ec9b80a4f5b0cb6d4dc70360a1 Mon Sep 17 00:00:00 2001 From: Alexander Ivchenko Date: Wed, 15 Oct 2014 11:02:02 +0000 Subject: [PATCH] AVX-512. 52.1/n. Add vec2mask and mask2vec insn. gcc/ * config/i386/predicates.md (define_predicate "constm1_operand"): New. * config/i386/sse.md (define_c_enum "unspec"): Add UNSPEC_CVTINT2MASK. (define_insn "_cvt2mask"): New. (define_insn "_cvt2mask"): Ditto. (define_expand "_cvtmask2"): Ditto. (define_insn "*_cvtmask2"): Ditto. (define_expand "_cvtmask2"): Ditto. (define_insn "*_cvtmask2"): Ditto. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin From-SVN: r216254 --- gcc/ChangeLog | 19 ++++++++++ gcc/config/i386/predicates.md | 9 +++++ gcc/config/i386/sse.md | 67 +++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 96b1e961d98..283c0d302cd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2014-10-15 Alexander Ivchenko + Maxim Kuznetsov + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/predicates.md (define_predicate "constm1_operand"): New. + * config/i386/sse.md + (define_c_enum "unspec"): Add UNSPEC_CVTINT2MASK. + (define_insn "_cvt2mask"): New. + (define_insn "_cvt2mask"): Ditto. + (define_expand "_cvtmask2"): Ditto. + (define_insn "*_cvtmask2"): Ditto. + (define_expand "_cvtmask2"): Ditto. + (define_insn "*_cvtmask2"): Ditto. + 2014-10-15 Renlin Li * config/aarch64/aarch64.h (ARM_DEFAULT_PCS, arm_pcs_variant): Delete. diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 690bed5f70b..9566884ee4f 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -618,6 +618,15 @@ return op == CONST0_RTX (mode); }) +;; Match -1. +(define_predicate "constm1_operand" + (match_code "const_int,const_double,const_vector") +{ + if (mode == VOIDmode) + mode = GET_MODE (op); + return op == CONSTM1_RTX (mode); +}) + ;; Match one or vector filled with ones. (define_predicate "const1_operand" (match_code "const_int,const_double,const_vector") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index fa2babf3f8e..018702afca8 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -135,6 +135,7 @@ UNSPEC_PMADDWD512 UNSPEC_PSHUFHW UNSPEC_PSHUFLW + UNSPEC_CVTINT2MASK ;; For AVX512DQ support UNSPEC_REDUCE @@ -4960,6 +4961,72 @@ (set_attr "prefix" "evex") (set_attr "mode" "V8DF")]) +(define_insn "_cvt2mask" + [(set (match_operand: 0 "register_operand" "=Yk") + (unspec: + [(match_operand:VI12_AVX512VL 1 "register_operand" "v")] + UNSPEC_CVTINT2MASK))] + "TARGET_AVX512BW" + "vpmov2m\t{%1, %0|%0, %1}" + [(set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "_cvt2mask" + [(set (match_operand: 0 "register_operand" "=Yk") + (unspec: + [(match_operand:VI48_AVX512VL 1 "register_operand" "v")] + UNSPEC_CVTINT2MASK))] + "TARGET_AVX512DQ" + "vpmov2m\t{%1, %0|%0, %1}" + [(set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_expand "_cvtmask2" + [(set (match_operand:VI12_AVX512VL 0 "register_operand") + (vec_merge:VI12_AVX512VL + (match_dup 2) + (match_dup 3) + (match_operand: 1 "register_operand")))] + "TARGET_AVX512BW" + { + operands[2] = CONSTM1_RTX (mode); + operands[3] = CONST0_RTX (mode); + }) + +(define_insn "*_cvtmask2" + [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI12_AVX512VL + (match_operand:VI12_AVX512VL 2 "constm1_operand") + (match_operand:VI12_AVX512VL 3 "const0_operand") + (match_operand: 1 "register_operand" "Yk")))] + "TARGET_AVX512BW" + "vpmovm2\t{%1, %0|%0, %1}" + [(set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_expand "_cvtmask2" + [(set (match_operand:VI48_AVX512VL 0 "register_operand") + (vec_merge:VI48_AVX512VL + (match_dup 2) + (match_dup 3) + (match_operand: 1 "register_operand")))] + "TARGET_AVX512DQ" + "{ + operands[2] = CONSTM1_RTX (mode); + operands[3] = CONST0_RTX (mode); + }") + +(define_insn "*_cvtmask2" + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI48_AVX512VL + (match_operand:VI48_AVX512VL 2 "constm1_operand") + (match_operand:VI48_AVX512VL 3 "const0_operand") + (match_operand: 1 "register_operand" "Yk")))] + "TARGET_AVX512DQ" + "vpmovm2\t{%1, %0|%0, %1}" + [(set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "sse2_cvtps2pd" [(set (match_operand:V2DF 0 "register_operand" "=v") (float_extend:V2DF -- 2.30.2