From 2bf68f5467e85cc46d600f2970ed07e0de8d4a0c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 7 Mar 2020 21:07:54 +0000 Subject: [PATCH] link in power field decoder --- src/decoder/power_decoder.py | 12 +++++++++++- src/decoder/power_fieldsn.py | 1 + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/decoder/power_decoder.py b/src/decoder/power_decoder.py index 446f6d38..5b5e7103 100644 --- a/src/decoder/power_decoder.py +++ b/src/decoder/power_decoder.py @@ -59,6 +59,8 @@ from power_enums import (Function, Form, InternalOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, get_csv, single_bit_flags, get_signal_name, default_values) from collections import namedtuple +from power_fields import DecodeFields +from power_fieldsn import SigDecode, SignalBitRange Subdecoder = namedtuple("Subdecoder", ["pattern", "opcodes", "opint", "bitsel", "suffix", "subdecoders"]) @@ -224,6 +226,14 @@ class PowerDecoder(Elaboratable): return [self.opcode_in] + self.op.ports() +class TopPowerDecoder(PowerDecoder, DecodeFields): + + def __init__(self, width, dec): + PowerDecoder.__init__(self, width, dec) + DecodeFields.__init__(self, SignalBitRange, [self.opcode_in]) + self.create_specs() + + def create_pdecode(): # minor 19 has extra patterns @@ -255,7 +265,7 @@ def create_pdecode(): dec.append(Subdecoder(pattern=None, opint=False, opcodes=opcodes, bitsel=(0, 32), suffix=None, subdecoders=[])) - return PowerDecoder(32, dec) + return TopPowerDecoder(32, dec) if __name__ == '__main__': diff --git a/src/decoder/power_fieldsn.py b/src/decoder/power_fieldsn.py index e48aee6e..e603bbd3 100644 --- a/src/decoder/power_fieldsn.py +++ b/src/decoder/power_fieldsn.py @@ -3,6 +3,7 @@ from power_fields import DecodeFields, BitRange from nmigen import Module, Elaboratable, Signal, Cat from nmigen.cli import rtlil + class SignalBitRange(BitRange): def __init__(self, signal): BitRange.__init__(self) -- 2.30.2