From 2c0404aeea0c2791349a630b30ed205d6dd17322 Mon Sep 17 00:00:00 2001
From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Tue, 30 Jun 2020 19:28:34 +0200
Subject: [PATCH] Build nMigen gateware in a specific folder

---
 gram/simulation/.gitignore   | 4 ++--
 gram/simulation/runsimsoc.sh | 2 +-
 gram/simulation/simsoc.py    | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/gram/simulation/.gitignore b/gram/simulation/.gitignore
index 81cd12c..39b62c5 100644
--- a/gram/simulation/.gitignore
+++ b/gram/simulation/.gitignore
@@ -3,8 +3,8 @@ simcrg
 simsoc
 
 # nMigen generated files
-simcrg.v
-simsoc.v
+build/
+build_simsoc/
 
 # Simulation output
 *.vcd
diff --git a/gram/simulation/runsimsoc.sh b/gram/simulation/runsimsoc.sh
index 78b13aa..9321c40 100755
--- a/gram/simulation/runsimsoc.sh
+++ b/gram/simulation/runsimsoc.sh
@@ -4,7 +4,7 @@ set -e
 LIB_DIR=/usr/local/diamond/3.11_x64/ispfpga/verilog/data/ecp5u
 
 python simsoc.py
-iverilog -Wall -g2012 -s simsoctb -o simsoc simsoctb.v build/top.debug.v dram_model/ddr3.v ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/EHXPLLL.v ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v \
+iverilog -Wall -g2012 -s simsoctb -o simsoc simsoctb.v build_simsoc/top.debug.v dram_model/ddr3.v ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/EHXPLLL.v ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v \
 	${LIB_DIR}/FD1S3AX.v ${LIB_DIR}/SGSR.v ${LIB_DIR}/ODDRX2F.v ${LIB_DIR}/ODDRX2DQA.v ${LIB_DIR}/DELAYF.v ${LIB_DIR}/BB.v ${LIB_DIR}/OB.v ${LIB_DIR}/IB.v \
 	${LIB_DIR}/DQSBUFM.v ${LIB_DIR}/UDFDL5_UDP_X.v ${LIB_DIR}/TSHX2DQSA.v ${LIB_DIR}/TSHX2DQA.v ${LIB_DIR}/ODDRX2DQSB.v ${LIB_DIR}/IDDRX2DQA.v DDRDLLA.patched.v \
 	${LIB_DIR}/CLKDIVF.v
diff --git a/gram/simulation/simsoc.py b/gram/simulation/simsoc.py
index ffcf961..19d57bd 100644
--- a/gram/simulation/simsoc.py
+++ b/gram/simulation/simsoc.py
@@ -276,4 +276,4 @@ if __name__ == "__main__":
         ddr_addr=0x10000000)
 
     soc.build(do_build=True)
-    platform.build(soc)
+    platform.build(soc, build_dir="build_simsoc")
-- 
2.30.2