From 2c43a21687b861bae462bea555c5875a4d0a91c8 Mon Sep 17 00:00:00 2001 From: Michael LeBeane Date: Tue, 13 Sep 2016 23:18:34 -0400 Subject: [PATCH] x86: Force strict ordering for memory mapped m5ops Normal MMAPPED_IPR requests are allowed to execute speculatively under the assumption that they have no side effects. The special case of m5ops that are treated like MMAPPED_IPR should not be allowed to execute speculatively, since they can have side-effects. Adding the STRICT_ORDER flag to these requests blocks execution until the associated instruction hits the ROB head. --- src/arch/x86/tlb.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index be43cb06e..0e0878669 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -235,7 +235,8 @@ TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const if (m5opRange.contains(paddr)) { if (m5opRange.contains(paddr)) { - req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR); + req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR | + Request::STRICT_ORDER); req->setPaddr(GenericISA::iprAddressPseudoInst( (paddr >> 8) & 0xFF, paddr & 0xFF)); -- 2.30.2