From 2c43f6f7dca84720b36fc5c6a63e1a708cdcc9aa Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 28 Dec 2018 15:58:28 +0100 Subject: [PATCH] targets/ulx3s: use pll for phase shift, enable refresh, memtest ok --- litex/boards/targets/ulx3s.py | 37 +++++++++-------------------------- 1 file changed, 9 insertions(+), 28 deletions(-) diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 4c60974f..76a4c067 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -13,47 +13,33 @@ from litex.soc.integration.builder import * from litedram.modules import MT48LC16M16 from litedram.phy import GENSDRPHY -from litedram.core.controller import ControllerSettings class _CRG(Module): def __init__(self, platform): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys_ps = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # # clk / rst clk25 = platform.request("clk25") rst = platform.request("rst") - platform.add_period_constraint(clk25, 40.0) # pll self.submodules.pll = pll = ECP5PLL() self.comb += pll.reset.eq(rst) pll.register_clkin(clk25, 25e6) - pll.create_clkout(self.cd_sys, 50e6) + pll.create_clkout(self.cd_sys, 50e6, phase=11) + pll.create_clkout(self.cd_sys_ps, 50e6, phase=20) # FIXME: AsyncResetSynchronizer needs FD1S3BX support. #self.specials += AsyncResetSynchronizer(self.cd_sys, rst) self.comb += self.cd_sys.rst.eq(rst) + platform.add_period_constraint(self.cd_sys.clk, 20.0) + platform.add_period_constraint(self.cd_sys_ps.clk, 20.0) - # sys_clk phase shifted (for sdram) - sdram_ps_clk = self.cd_sys.clk - # FIXME: phase shift with luts, needs PLL support. - sdram_ps_luts = 5 - for i in range(sdram_ps_luts): - new_sdram_ps_clk = Signal() - self.specials += Instance("LUT4", - p_INIT=2, - i_A=sdram_ps_clk, - i_B=0, - i_C=0, - i_D=0, - o_Z=new_sdram_ps_clk) - sdram_ps_clk = new_sdram_ps_clk - self.comb += self.cd_sys_ps.clk.eq(sdram_ps_clk) - sdram_clock = platform.request("sdram_clock") - self.comb += sdram_clock.eq(sdram_ps_clk) + # sdram clock + self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) # Stop ESP32 from resetting FPGA wifi_gpio0 = platform.request("wifi_gpio0") @@ -63,9 +49,8 @@ class _CRG(Module): class BaseSoC(SoCSDRAM): def __init__(self, **kwargs): platform = ulx3s.Platform(toolchain="trellis") - sys_clk_freq = int(25e6) + sys_clk_freq = int(50e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - l2_size=32, integrated_rom_size=0x8000, **kwargs) @@ -76,10 +61,7 @@ class BaseSoC(SoCSDRAM): sdram_module = MT48LC16M16(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, - sdram_module.timing_settings, - controller_settings=ControllerSettings( - with_refresh=False)) # FIXME - + sdram_module.timing_settings) def main(): parser = argparse.ArgumentParser(description="LiteX SoC port to the ULX3S") @@ -91,6 +73,5 @@ def main(): builder = Builder(soc, **builder_argdict(args)) builder.build() - if __name__ == "__main__": main() -- 2.30.2