From 2c4b89639ffdcef19dd92e88d9cc4a983ccd7083 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 16 Mar 2020 11:44:39 +0100 Subject: [PATCH] soc/cores/clock: make sure specific clkoutn_divide_range is only used as a fallback solution. --- litex/soc/cores/clock.py | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index 5b68ec59..195fc7ae 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -126,16 +126,20 @@ class XilinxClocking(Module, AutoCSR): vco_freq <= vco_freq_max*(1 - self.vco_margin)): for n, (clk, f, p, m) in sorted(self.clkouts.items()): valid = False - d_range = self.clkout_divide_range - d_range = getattr(self, "clkout{}_divide_range".format(n), d_range) - for d in clkdiv_range(*d_range): - clk_freq = vco_freq/d - if abs(clk_freq - f) <= f*m: - config["clkout{}_freq".format(n)] = clk_freq - config["clkout{}_divide".format(n)] = d - config["clkout{}_phase".format(n)] = p - valid = True - break + d_ranges = [self.clkout_divide_range] + if getattr(self, "clkout{}_divide_range".format(n), None) is not None: + d_ranges += [getattr(self, "clkout{}_divide_range".format(n))] + for d_range in d_ranges: + for d in clkdiv_range(*d_range): + clk_freq = vco_freq/d + if abs(clk_freq - f) <= f*m: + config["clkout{}_freq".format(n)] = clk_freq + config["clkout{}_divide".format(n)] = d + config["clkout{}_phase".format(n)] = p + valid = True + break + if valid: + break if not valid: all_valid = False else: -- 2.30.2