From 2c5db2b0764253ec8319b8f08ed8cdceea4022ce Mon Sep 17 00:00:00 2001
From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Wed, 22 Nov 2023 14:10:23 +0000
Subject: [PATCH] Added English language description for addi, addis and
 addpcis instruction

---
 openpower/isa/fixedarith.mdwn | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn
index 4044ded9..818a28b2 100644
--- a/openpower/isa/fixedarith.mdwn
+++ b/openpower/isa/fixedarith.mdwn
@@ -12,6 +12,10 @@ Pseudo-code:
 
     RT <- (RA|0) + EXTS(SI)
 
+Description:
+
+    The sum (RA|0) + SI is placed into register RT.
+
 Special Registers Altered:
 
     None
@@ -26,6 +30,11 @@ Pseudo-code:
 
     RT <- (RA|0) + EXTS(SI || [0]*16)
 
+Description:
+
+    The sum (RA|0) + (SI || 0x0000) is placed into register
+    RT.
+
 Special Registers Altered:
 
     None
@@ -41,6 +50,11 @@ Pseudo-code:
     D <- d0||d1||d2
     RT <- NIA + EXTS(D || [0]*16)
 
+Description:
+
+    The sum of NIA + (D || 0x0000) is placed into register
+    RT.
+
 Special Registers Altered:
 
     None
-- 
2.30.2