From 2c5fe6f95e64a5a97d56cccc6b8b5417cdd981ae Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 4 Nov 2009 16:57:01 -0800 Subject: [PATCH] build: fix compile problems pointed out by gcc 4.4 --- src/arch/arm/insts/static_inst.cc | 9 ++--- src/arch/mips/dsp.cc | 4 ++- src/arch/x86/interrupts.cc | 2 +- src/arch/x86/isa.cc | 2 +- src/arch/x86/system.cc | 2 +- src/base/bigint.cc | 4 +-- src/base/bigint.hh | 5 +-- src/base/inet.cc | 1 + src/base/remote_gdb.cc | 1 + src/base/types.hh | 1 + src/cpu/inorder/resource.hh | 1 + src/cpu/inst_seq.hh | 2 ++ src/cpu/legiontrace.cc | 4 ++- src/dev/sparc/iob.cc | 14 ++++---- src/dev/x86/i82094aa.cc | 2 +- src/kern/linux/linux.cc | 1 + src/mem/physical.cc | 1 + src/mem/ruby/common/Address.hh | 2 +- src/mem/ruby/network/orion/power_utils.cc | 42 +++++++++++++---------- src/sim/eventq.hh | 2 +- src/sim/process.cc | 2 ++ src/sim/syscall_emul.cc | 3 +- 22 files changed, 64 insertions(+), 43 deletions(-) diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index df2d5de25..5181041d0 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -29,6 +29,7 @@ #include "arch/arm/insts/static_inst.hh" #include "base/condcodes.hh" +#include "base/cprintf.hh" #include "base/loader/symtab.hh" namespace ArmISA @@ -62,7 +63,7 @@ ArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt, else return (base << (32 - shamt)) | (base >> shamt); default: - fprintf(stderr, "Unhandled shift type\n"); + ccprintf(std::cerr, "Unhandled shift type\n"); exit(1); break; } @@ -101,7 +102,7 @@ ArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt, else return (base << (32 - shamt)) | (base >> shamt); default: - fprintf(stderr, "Unhandled shift type\n"); + ccprintf(std::cerr, "Unhandled shift type\n"); exit(1); break; } @@ -141,7 +142,7 @@ ArmStaticInst::shift_carry_imm(uint32_t base, uint32_t shamt, else return (base >> (shamt - 1)) & 1; default: - fprintf(stderr, "Unhandled shift type\n"); + ccprintf(std::cerr, "Unhandled shift type\n"); exit(1); break; } @@ -182,7 +183,7 @@ ArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt, shamt = 32; return (base >> (shamt - 1)) & 1; default: - fprintf(stderr, "Unhandled shift type\n"); + ccprintf(std::cerr, "Unhandled shift type\n"); exit(1); break; } diff --git a/src/arch/mips/dsp.cc b/src/arch/mips/dsp.cc index 6e4f7afea..b8b02ae9e 100755 --- a/src/arch/mips/dsp.cc +++ b/src/arch/mips/dsp.cc @@ -463,6 +463,8 @@ MipsISA::dspMuleq(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl) uint64_t b_values[SIMD_MAX_VALS]; uint64_t c_values[SIMD_MAX_VALS]; + memset(c_values, 0, sizeof(c_values)); + simdUnpack(a, a_values, SIMD_FMT_PH, SIGNED); simdUnpack(b, b_values, SIMD_FMT_PH, SIGNED); @@ -743,7 +745,7 @@ MipsISA::dspMulsaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int nvals = SIMD_NVALS[fmt]; uint64_t a_values[SIMD_MAX_VALS]; uint64_t b_values[SIMD_MAX_VALS]; - int64_t temp[2]; + int64_t temp[2] = {0, 0}; uint32_t ouflag = 0; simdUnpack(a, a_values, fmt, SIGNED); diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc index 1b7933036..1b83c6649 100644 --- a/src/arch/x86/interrupts.cc +++ b/src/arch/x86/interrupts.cc @@ -500,7 +500,7 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; // Record that an IPI is being sent. low.deliveryStatus = 1; - TriggerIntMessage message; + TriggerIntMessage message = 0; message.destination = high.destination; message.vector = low.vector; message.deliveryMode = low.deliveryMode; diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc index 06a656efc..47d24ed1e 100644 --- a/src/arch/x86/isa.cc +++ b/src/arch/x86/isa.cc @@ -41,7 +41,7 @@ void ISA::updateHandyM5Reg(Efer efer, CR0 cr0, SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags) { - HandyM5Reg m5reg; + HandyM5Reg m5reg = 0; if (efer.lma) { m5reg.mode = LongMode; if (csAttr.longMode) diff --git a/src/arch/x86/system.cc b/src/arch/x86/system.cc index 1594cc375..31183f2f9 100644 --- a/src/arch/x86/system.cc +++ b/src/arch/x86/system.cc @@ -211,7 +211,7 @@ X86System::startup() numGDTEntries++; - SegSelector ds; + SegSelector ds = 0; ds.si = numGDTEntries - 1; tc->setMiscReg(MISCREG_DS, (MiscReg)ds); diff --git a/src/base/bigint.cc b/src/base/bigint.cc index ce9942c9c..d741e1f7b 100644 --- a/src/base/bigint.cc +++ b/src/base/bigint.cc @@ -28,10 +28,10 @@ * Authors: Gabe Black */ -#include "base/bigint.hh" - #include +#include "base/bigint.hh" + using namespace std; ostream & operator << (ostream & os, const Twin64_t & t) diff --git a/src/base/bigint.hh b/src/base/bigint.hh index d60684231..a4e8738d3 100644 --- a/src/base/bigint.hh +++ b/src/base/bigint.hh @@ -28,10 +28,11 @@ * Authors: Ali Saidi */ -#include "base/misc.hh" - #include +#include "base/misc.hh" +#include "base/types.hh" + #ifndef __BASE_BIGINT_HH__ #define __BASE_BIGINT_HH__ // Create a couple of large int types for atomic reads diff --git a/src/base/inet.cc b/src/base/inet.cc index 898a189ef..1a280e993 100644 --- a/src/base/inet.cc +++ b/src/base/inet.cc @@ -28,6 +28,7 @@ * Authors: Nathan Binkert */ +#include #include #include diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc index c54379c23..68747b3d1 100644 --- a/src/base/remote_gdb.cc +++ b/src/base/remote_gdb.cc @@ -118,6 +118,7 @@ #include +#include #include #include diff --git a/src/base/types.hh b/src/base/types.hh index 1a6db9fbb..0c10fac64 100644 --- a/src/base/types.hh +++ b/src/base/types.hh @@ -55,6 +55,7 @@ typedef int64_t Counter; * @note using an unsigned breaks the cache. */ typedef int64_t Tick; +typedef uint64_t UTick; const Tick MaxTick = LL(0x7fffffffffffffff); diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh index 7935e5517..605b7f690 100644 --- a/src/cpu/inorder/resource.hh +++ b/src/cpu/inorder/resource.hh @@ -36,6 +36,7 @@ #include #include +#include "base/types.hh" #include "cpu/inst_seq.hh" #include "cpu/inorder/inorder_dyn_inst.hh" #include "cpu/inorder/pipeline_traits.hh" diff --git a/src/cpu/inst_seq.hh b/src/cpu/inst_seq.hh index 21e04ed25..b5feaf584 100644 --- a/src/cpu/inst_seq.hh +++ b/src/cpu/inst_seq.hh @@ -32,6 +32,8 @@ #ifndef __STD_TYPES_HH__ #define __STD_TYPES_HH__ +#include "base/types.hh" + // inst sequence type, used to order instructions in the ready list, // if this rolls over the ready list order temporarily will get messed // up, but execution will continue and complete correctly diff --git a/src/cpu/legiontrace.cc b/src/cpu/legiontrace.cc index f1980c713..1390d0807 100644 --- a/src/cpu/legiontrace.cc +++ b/src/cpu/legiontrace.cc @@ -41,10 +41,12 @@ #error Legion tracing only works in full system! #endif -#include #include #include +#include +#include + #include "arch/sparc/predecoder.hh" #include "arch/sparc/registers.hh" #include "arch/sparc/utility.hh" diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc index 4543dd07b..40f856d8a 100644 --- a/src/dev/sparc/iob.cc +++ b/src/dev/sparc/iob.cc @@ -90,20 +90,18 @@ void Iob::readIob(PacketPtr pkt) { Addr accessAddr = pkt->getAddr() - iobManAddr; - int index; - uint64_t data; if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) { - index = (accessAddr - IntManAddr) >> 3; - data = intMan[index].cpu << 8 | intMan[index].vector << 0; + int index = (accessAddr - IntManAddr) >> 3; + uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0; pkt->set(data); return; } if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) { - index = (accessAddr - IntManAddr) >> 3; - data = intCtl[index].mask ? 1 << 2 : 0 | - intCtl[index].pend ? 1 << 0 : 0; + int index = (accessAddr - IntCtlAddr) >> 3; + uint64_t data = intCtl[index].mask ? 1 << 2 : 0 | + intCtl[index].pend ? 1 << 0 : 0; pkt->set(data); return; } @@ -199,7 +197,7 @@ Iob::writeIob(PacketPtr pkt) } if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) { - index = (accessAddr - IntManAddr) >> 3; + index = (accessAddr - IntCtlAddr) >> 3; data = pkt->get(); intCtl[index].mask = bits(data,2,2); if (bits(data,1,1)) diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc index ed936d0cb..591fee6a4 100644 --- a/src/dev/x86/i82094aa.cc +++ b/src/dev/x86/i82094aa.cc @@ -151,7 +151,7 @@ X86ISA::I82094AA::signalInterrupt(int line) DPRINTF(I82094AA, "Entry was masked.\n"); return; } else { - TriggerIntMessage message; + TriggerIntMessage message = 0; message.destination = entry.dest; if (entry.deliveryMode == DeliveryMode::ExtInt) { assert(extIntPic); diff --git a/src/kern/linux/linux.cc b/src/kern/linux/linux.cc index abe7c0b75..72f1832b8 100644 --- a/src/kern/linux/linux.cc +++ b/src/kern/linux/linux.cc @@ -28,6 +28,7 @@ * Authors: Ali Saidi */ +#include #include #include "cpu/thread_context.hh" diff --git a/src/mem/physical.cc b/src/mem/physical.cc index be4086cd9..121a6e447 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -36,6 +36,7 @@ #include #include +#include #include #include diff --git a/src/mem/ruby/common/Address.hh b/src/mem/ruby/common/Address.hh index c48152354..88cd2668a 100644 --- a/src/mem/ruby/common/Address.hh +++ b/src/mem/ruby/common/Address.hh @@ -148,7 +148,7 @@ inline physical_address_t Address::bitSelect(int small, int big) const // rips bits inclusive { physical_address_t mask; - assert(big >= small); + assert((unsigned)big >= (unsigned)small); if (big >= ADDRESS_WIDTH - 1) { return (m_address >> small); diff --git a/src/mem/ruby/network/orion/power_utils.cc b/src/mem/ruby/network/orion/power_utils.cc index bc69c3cc7..358e13c6f 100644 --- a/src/mem/ruby/network/orion/power_utils.cc +++ b/src/mem/ruby/network/orion/power_utils.cc @@ -30,6 +30,7 @@ #include #include +#include "base/types.hh" #include "mem/ruby/network/orion/parm_technology.hh" #include "mem/ruby/network/orion/power_utils.hh" @@ -39,11 +40,11 @@ static char h_tab[256] = {0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8}; -static unsigned SIM_power_Hamming_slow( unsigned long int old_val, unsigned long int new_val, unsigned long int mask ) +static uint32_t SIM_power_Hamming_slow( uint64_t old_val, uint64_t new_val, uint64_t mask ) { /* old slow code, I don't understand the new fast code though */ - /* unsigned long int dist; - unsigned Hamming = 0; + /* uint64_t dist; + uint32_t Hamming = 0; dist = ( old_val ^ new_val ) & mask; mask = (mask >> 1) + 1; @@ -58,7 +59,7 @@ static unsigned SIM_power_Hamming_slow( unsigned long int old_val, unsigned long #define TWO(k) (BIGONE << (k)) #define CYCL(k) (BIGNONE/(1 + (TWO(TWO(k))))) #define BSUM(x,k) ((x)+=(x) >> TWO(k), (x) &= CYCL(k)) - unsigned long int x; + uint64_t x; x = (old_val ^ new_val) & mask; x = (x & CYCL(0)) + ((x>>TWO(0)) & CYCL(0)); @@ -74,7 +75,7 @@ static unsigned SIM_power_Hamming_slow( unsigned long int old_val, unsigned long int SIM_power_init(void) { - unsigned i; + uint32_t i; /* initialize Hamming distance table */ for (i = 0; i < 256; i++) @@ -84,14 +85,16 @@ int SIM_power_init(void) } -/* assume unsigned long int is unsigned64_t */ -unsigned SIM_power_Hamming(unsigned long int old_val, unsigned long int new_val, unsigned long int mask) + +uint32_t +SIM_power_Hamming(uint64_t old_val, uint64_t new_val, uint64_t mask) { - union { - unsigned long int x; - char id[8]; - } u; - unsigned rval; + union { + uint64_t x; + uint64_t id[8]; + } u; + + uint32_t rval; u.x = (old_val ^ new_val) & mask; @@ -108,10 +111,12 @@ unsigned SIM_power_Hamming(unsigned long int old_val, unsigned long int new_val, } -unsigned SIM_power_Hamming_group(unsigned long int d1_new, unsigned long int d1_old, unsigned long int d2_new, unsigned long int d2_old, unsigned width, unsigned n_grp) +uint32_t +SIM_power_Hamming_group(uint64_t d1_new, uint64_t d1_old, uint64_t d2_new, + uint64_t d2_old, uint32_t width, uint32_t n_grp) { - unsigned rval = 0; - unsigned long int g1_new, g1_old, g2_new, g2_old, mask; + uint32_t rval = 0; + uint64_t g1_new, g1_old, g2_new, g2_old, mask; mask = HAMM_MASK(width); @@ -146,11 +151,12 @@ double logtwo(double x) return log10(x)/log10(2); } -unsigned SIM_power_logtwo(unsigned long int x) +uint32_t +SIM_power_logtwo(uint64_t x) { - unsigned rval = 0; + uint32_t rval = 0; - while (x >> rval && rval < sizeof(unsigned long int) << 3) rval++; + while (x >> rval && rval < sizeof(uint64_t) << 3) rval++; if (x == (BIGONE << rval - 1)) rval--; return rval; diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh index 29efdeb6f..92c38142c 100644 --- a/src/sim/eventq.hh +++ b/src/sim/eventq.hh @@ -471,7 +471,7 @@ class EventWrapper : public Event inline void EventQueue::schedule(Event *event, Tick when) { - assert(when >= curTick); + assert((UTick)when >= (UTick)curTick); assert(!event->scheduled()); #ifdef EVENTQ_DEBUG assert((event->flags & Event::Initialized) == Event::Initialized); diff --git a/src/sim/process.cc b/src/sim/process.cc index e71d6441f..343d2ad5a 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -32,6 +32,8 @@ #include #include + +#include #include #include "arch/remote_gdb.hh" diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc index cc8d99bcd..7cffffcf1 100644 --- a/src/sim/syscall_emul.cc +++ b/src/sim/syscall_emul.cc @@ -32,8 +32,9 @@ #include #include -#include +#include #include +#include #include "sim/syscall_emul.hh" #include "base/chunk_generator.hh" -- 2.30.2