From 2c98350fcb269a653b11f73ca0175679aa29977a Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 3 Dec 2019 18:06:24 +0000 Subject: [PATCH] Mark constant-sized objects as addressable if they have poly-int accesses If SVE code is written for a specific vector length, it might load from or store to fixed-sized objects. This needs to work even without -msve-vector-bits=N (which should never be needed for correctness). There's no way of handling a direct poly-int sized reference to a fixed-size register; it would have to go via memory. And in that case it's more efficient to mark the fixed-size object as addressable from the outset, like we do for array references with non-constant indices. 2019-12-03 Richard Sandiford gcc/ * cfgexpand.c (discover_nonconstant_array_refs_r): If an access with POLY_INT_CST size is made to a fixed-size object, force the object to live in memory. gcc/testsuite/ * gcc.target/aarch64/sve/acle/general/deref_1.c: New test. From-SVN: r278941 --- gcc/ChangeLog | 6 +++++ gcc/cfgexpand.c | 15 +++++++++++ gcc/testsuite/ChangeLog | 4 +++ .../aarch64/sve/acle/general/deref_1.c | 25 +++++++++++++++++++ 4 files changed, 50 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/deref_1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2902cdc7344..1b246171d46 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-12-03 Richard Sandiford + + * cfgexpand.c (discover_nonconstant_array_refs_r): If an access + with POLY_INT_CST size is made to a fixed-size object, force the + object to live in memory. + 2019-12-03 Andrew Stubbs * config/gcn/gcn-valu.md: Change "vcondu" patterns to use VEC_1REG_MODE diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c index e8bed2504bf..bb31fef7014 100644 --- a/gcc/cfgexpand.c +++ b/gcc/cfgexpand.c @@ -6133,6 +6133,21 @@ discover_nonconstant_array_refs_r (tree * tp, int *walk_subtrees, *walk_subtrees = 0; } + /* References of size POLY_INT_CST to a fixed-size object must go + through memory. It's more efficient to force that here than + to create temporary slots on the fly. */ + else if ((TREE_CODE (t) == MEM_REF || TREE_CODE (t) == TARGET_MEM_REF) + && TYPE_SIZE (TREE_TYPE (t)) + && POLY_INT_CST_P (TYPE_SIZE (TREE_TYPE (t)))) + { + tree base = get_base_address (t); + if (base + && DECL_P (base) + && DECL_MODE (base) != BLKmode + && GET_MODE_SIZE (DECL_MODE (base)).is_constant ()) + TREE_ADDRESSABLE (base) = 1; + *walk_subtrees = 0; + } return NULL_TREE; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index cc8ff79cbc2..028755bb51a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-12-03 Richard Sandiford + + * gcc.target/aarch64/sve/acle/general/deref_1.c: New test. + 2019-12-03 Marek Polacek PR c++/91363 - P0960R3: Parenthesized initialization of aggregates. diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/deref_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/deref_1.c new file mode 100644 index 00000000000..99d831936a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/deref_1.c @@ -0,0 +1,25 @@ +/* { dg-options "-O2" } */ + +#include + +uint64_t +f1 (int32_t *x, int32_t *y) +{ + union { uint64_t x; char c[8]; } u; + svbool_t pg = svptrue_b32 (); + *(svbool_t *)&u.c[0] = svcmpeq (pg, svld1 (pg, x), 0); + *(svbool_t *)&u.c[4] = svcmpeq (pg, svld1 (pg, y), 1); + return u.x; +} + +typedef unsigned int v4si __attribute__((vector_size(16))); + +/* The aliasing is somewhat dubious here, but it must compile. */ + +v4si +f2 (void) +{ + v4si res; + *(svuint32_t *) &res = svindex_u32 (0, 1); + return res; +} -- 2.30.2