From 2cb47355d4b3e8021a88f68f7a5f33ce46ff51b0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 28 Jan 2014 06:55:47 +0100 Subject: [PATCH] Renamed manual/FILES_* directories --- manual/{FILES_Eval => CHAPTER_Eval}/grep-it.sh | 0 manual/{FILES_Eval => CHAPTER_Eval}/openmsp430.prj | 0 .../{FILES_Eval => CHAPTER_Eval}/openmsp430_ys.prj | 0 manual/{FILES_Eval => CHAPTER_Eval}/or1200.prj | 0 manual/{FILES_Eval => CHAPTER_Eval}/or1200_ys.prj | 0 manual/{FILES_Eval => CHAPTER_Eval}/run-it.sh | 0 manual/{FILES_Eval => CHAPTER_Eval}/settings.xst | 0 manual/CHAPTER_Prog.tex | 6 +++--- manual/{FILES_Prog => CHAPTER_Prog}/Makefile | 0 manual/{FILES_Prog => CHAPTER_Prog}/stubnets.cc | 0 manual/{FILES_Prog => CHAPTER_Prog}/test.v | 0 manual/CHAPTER_StateOfTheArt.tex | 12 ++++++------ .../always01.v | 0 .../always01_pub.v | 0 .../always02.v | 0 .../always02_pub.v | 0 .../always03.v | 0 .../arrays01.v | 0 .../cmp_tbdata.c | 0 .../forgen01.v | 0 .../forgen02.v | 0 .../iverilog-0.8.7-buildfixes.patch | 0 .../mvsis-1.3.6-buildfixes.patch | 0 .../simlib_hana.v | 0 .../simlib_icarus.v | 0 .../simlib_yosys.v | 0 .../sis-1.3.6-buildfixes.patch | 0 .../synth.sh | 0 .../validate_tb.sh | 0 29 files changed, 9 insertions(+), 9 deletions(-) rename manual/{FILES_Eval => CHAPTER_Eval}/grep-it.sh (100%) rename manual/{FILES_Eval => CHAPTER_Eval}/openmsp430.prj (100%) rename manual/{FILES_Eval => CHAPTER_Eval}/openmsp430_ys.prj (100%) rename manual/{FILES_Eval => CHAPTER_Eval}/or1200.prj (100%) rename manual/{FILES_Eval => CHAPTER_Eval}/or1200_ys.prj (100%) rename manual/{FILES_Eval => CHAPTER_Eval}/run-it.sh (100%) rename manual/{FILES_Eval => CHAPTER_Eval}/settings.xst (100%) rename manual/{FILES_Prog => CHAPTER_Prog}/Makefile (100%) rename manual/{FILES_Prog => CHAPTER_Prog}/stubnets.cc (100%) rename manual/{FILES_Prog => CHAPTER_Prog}/test.v (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/always01.v (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/always01_pub.v (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/always02.v (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/always02_pub.v (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/always03.v (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/arrays01.v (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/cmp_tbdata.c (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/forgen01.v (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/forgen02.v (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/iverilog-0.8.7-buildfixes.patch (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/mvsis-1.3.6-buildfixes.patch (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/simlib_hana.v (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/simlib_icarus.v (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/simlib_yosys.v (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/sis-1.3.6-buildfixes.patch (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/synth.sh (100%) rename manual/{FILES_StateOfTheArt => CHAPTER_StateOfTheArt}/validate_tb.sh (100%) diff --git a/manual/FILES_Eval/grep-it.sh b/manual/CHAPTER_Eval/grep-it.sh similarity index 100% rename from manual/FILES_Eval/grep-it.sh rename to manual/CHAPTER_Eval/grep-it.sh diff --git a/manual/FILES_Eval/openmsp430.prj b/manual/CHAPTER_Eval/openmsp430.prj similarity index 100% rename from manual/FILES_Eval/openmsp430.prj rename to manual/CHAPTER_Eval/openmsp430.prj diff --git a/manual/FILES_Eval/openmsp430_ys.prj b/manual/CHAPTER_Eval/openmsp430_ys.prj similarity index 100% rename from manual/FILES_Eval/openmsp430_ys.prj rename to manual/CHAPTER_Eval/openmsp430_ys.prj diff --git a/manual/FILES_Eval/or1200.prj b/manual/CHAPTER_Eval/or1200.prj similarity index 100% rename from manual/FILES_Eval/or1200.prj rename to manual/CHAPTER_Eval/or1200.prj diff --git a/manual/FILES_Eval/or1200_ys.prj b/manual/CHAPTER_Eval/or1200_ys.prj similarity index 100% rename from manual/FILES_Eval/or1200_ys.prj rename to manual/CHAPTER_Eval/or1200_ys.prj diff --git a/manual/FILES_Eval/run-it.sh b/manual/CHAPTER_Eval/run-it.sh similarity index 100% rename from manual/FILES_Eval/run-it.sh rename to manual/CHAPTER_Eval/run-it.sh diff --git a/manual/FILES_Eval/settings.xst b/manual/CHAPTER_Eval/settings.xst similarity index 100% rename from manual/FILES_Eval/settings.xst rename to manual/CHAPTER_Eval/settings.xst diff --git a/manual/CHAPTER_Prog.tex b/manual/CHAPTER_Prog.tex index b6157aa1c..3918594a2 100644 --- a/manual/CHAPTER_Prog.tex +++ b/manual/CHAPTER_Prog.tex @@ -13,9 +13,9 @@ with an example module. \section{Example Module} -\lstinputlisting[title=stubnets.cc,numbers=left,frame=single,language=C++]{FILES_Prog/stubnets.cc} +\lstinputlisting[title=stubnets.cc,numbers=left,frame=single,language=C++]{CHAPTER_Prog/stubnets.cc} -\lstinputlisting[title=Makefile,numbers=left,frame=single,language=make]{FILES_Prog/Makefile} +\lstinputlisting[title=Makefile,numbers=left,frame=single,language=make]{CHAPTER_Prog/Makefile} -\lstinputlisting[title=test.v,numbers=left,frame=single,language=Verilog]{FILES_Prog/test.v} +\lstinputlisting[title=test.v,numbers=left,frame=single,language=Verilog]{CHAPTER_Prog/test.v} diff --git a/manual/FILES_Prog/Makefile b/manual/CHAPTER_Prog/Makefile similarity index 100% rename from manual/FILES_Prog/Makefile rename to manual/CHAPTER_Prog/Makefile diff --git a/manual/FILES_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc similarity index 100% rename from manual/FILES_Prog/stubnets.cc rename to manual/CHAPTER_Prog/stubnets.cc diff --git a/manual/FILES_Prog/test.v b/manual/CHAPTER_Prog/test.v similarity index 100% rename from manual/FILES_Prog/test.v rename to manual/CHAPTER_Prog/test.v diff --git a/manual/CHAPTER_StateOfTheArt.tex b/manual/CHAPTER_StateOfTheArt.tex index d6a5c9b18..7e62230ef 100644 --- a/manual/CHAPTER_StateOfTheArt.tex +++ b/manual/CHAPTER_StateOfTheArt.tex @@ -55,18 +55,18 @@ with a summary of the results. \begin{figure}[t!] \begin{minipage}{7.7cm} - \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/always01_pub.v} + \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always01_pub.v} \end{minipage} \hfill \begin{minipage}{7.7cm} - \lstinputlisting[frame=single,language=Verilog]{FILES_StateOfTheArt/always02_pub.v} + \lstinputlisting[frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always02_pub.v} \end{minipage} \caption{1st and 2nd Verilog always examples} \label{fig:StateOfTheArt_always12} \end{figure} \begin{figure}[!] - \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/always03.v} + \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always03.v} \caption{3rd Verilog always example} \label{fig:StateOfTheArt_always3} \end{figure} @@ -107,7 +107,7 @@ The first example is only using the most fundamental Verilog features. All tools under test were able to successfully synthesize this design. \begin{figure}[b!] - \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/arrays01.v} + \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/arrays01.v} \caption{Verilog array example} \label{fig:StateOfTheArt_arrays} \end{figure} @@ -155,7 +155,7 @@ For this design HANA, vl2m and ODIN-II generate error messages indicating that arrays are not supported. \begin{figure}[t!] - \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/forgen01.v} + \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/forgen01.v} \caption{Verilog for loop example} \label{fig:StateOfTheArt_for} \end{figure} @@ -171,7 +171,7 @@ by continuing tests on this aspect of Verilog synthesis such as synthesis of dua memories, correct handling of write collisions, and so forth. \begin{figure}[t!] - \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/forgen02.v} + \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/forgen02.v} \caption{Verilog generate example} \label{fig:StateOfTheArt_gen} \end{figure} diff --git a/manual/FILES_StateOfTheArt/always01.v b/manual/CHAPTER_StateOfTheArt/always01.v similarity index 100% rename from manual/FILES_StateOfTheArt/always01.v rename to manual/CHAPTER_StateOfTheArt/always01.v diff --git a/manual/FILES_StateOfTheArt/always01_pub.v b/manual/CHAPTER_StateOfTheArt/always01_pub.v similarity index 100% rename from manual/FILES_StateOfTheArt/always01_pub.v rename to manual/CHAPTER_StateOfTheArt/always01_pub.v diff --git a/manual/FILES_StateOfTheArt/always02.v b/manual/CHAPTER_StateOfTheArt/always02.v similarity index 100% rename from manual/FILES_StateOfTheArt/always02.v rename to manual/CHAPTER_StateOfTheArt/always02.v diff --git a/manual/FILES_StateOfTheArt/always02_pub.v b/manual/CHAPTER_StateOfTheArt/always02_pub.v similarity index 100% rename from manual/FILES_StateOfTheArt/always02_pub.v rename to manual/CHAPTER_StateOfTheArt/always02_pub.v diff --git a/manual/FILES_StateOfTheArt/always03.v b/manual/CHAPTER_StateOfTheArt/always03.v similarity index 100% rename from manual/FILES_StateOfTheArt/always03.v rename to manual/CHAPTER_StateOfTheArt/always03.v diff --git a/manual/FILES_StateOfTheArt/arrays01.v b/manual/CHAPTER_StateOfTheArt/arrays01.v similarity index 100% rename from manual/FILES_StateOfTheArt/arrays01.v rename to manual/CHAPTER_StateOfTheArt/arrays01.v diff --git a/manual/FILES_StateOfTheArt/cmp_tbdata.c b/manual/CHAPTER_StateOfTheArt/cmp_tbdata.c similarity index 100% rename from manual/FILES_StateOfTheArt/cmp_tbdata.c rename to manual/CHAPTER_StateOfTheArt/cmp_tbdata.c diff --git a/manual/FILES_StateOfTheArt/forgen01.v b/manual/CHAPTER_StateOfTheArt/forgen01.v similarity index 100% rename from manual/FILES_StateOfTheArt/forgen01.v rename to manual/CHAPTER_StateOfTheArt/forgen01.v diff --git a/manual/FILES_StateOfTheArt/forgen02.v b/manual/CHAPTER_StateOfTheArt/forgen02.v similarity index 100% rename from manual/FILES_StateOfTheArt/forgen02.v rename to manual/CHAPTER_StateOfTheArt/forgen02.v diff --git a/manual/FILES_StateOfTheArt/iverilog-0.8.7-buildfixes.patch b/manual/CHAPTER_StateOfTheArt/iverilog-0.8.7-buildfixes.patch similarity index 100% rename from manual/FILES_StateOfTheArt/iverilog-0.8.7-buildfixes.patch rename to manual/CHAPTER_StateOfTheArt/iverilog-0.8.7-buildfixes.patch diff --git a/manual/FILES_StateOfTheArt/mvsis-1.3.6-buildfixes.patch b/manual/CHAPTER_StateOfTheArt/mvsis-1.3.6-buildfixes.patch similarity index 100% rename from manual/FILES_StateOfTheArt/mvsis-1.3.6-buildfixes.patch rename to manual/CHAPTER_StateOfTheArt/mvsis-1.3.6-buildfixes.patch diff --git a/manual/FILES_StateOfTheArt/simlib_hana.v b/manual/CHAPTER_StateOfTheArt/simlib_hana.v similarity index 100% rename from manual/FILES_StateOfTheArt/simlib_hana.v rename to manual/CHAPTER_StateOfTheArt/simlib_hana.v diff --git a/manual/FILES_StateOfTheArt/simlib_icarus.v b/manual/CHAPTER_StateOfTheArt/simlib_icarus.v similarity index 100% rename from manual/FILES_StateOfTheArt/simlib_icarus.v rename to manual/CHAPTER_StateOfTheArt/simlib_icarus.v diff --git a/manual/FILES_StateOfTheArt/simlib_yosys.v b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v similarity index 100% rename from manual/FILES_StateOfTheArt/simlib_yosys.v rename to manual/CHAPTER_StateOfTheArt/simlib_yosys.v diff --git a/manual/FILES_StateOfTheArt/sis-1.3.6-buildfixes.patch b/manual/CHAPTER_StateOfTheArt/sis-1.3.6-buildfixes.patch similarity index 100% rename from manual/FILES_StateOfTheArt/sis-1.3.6-buildfixes.patch rename to manual/CHAPTER_StateOfTheArt/sis-1.3.6-buildfixes.patch diff --git a/manual/FILES_StateOfTheArt/synth.sh b/manual/CHAPTER_StateOfTheArt/synth.sh similarity index 100% rename from manual/FILES_StateOfTheArt/synth.sh rename to manual/CHAPTER_StateOfTheArt/synth.sh diff --git a/manual/FILES_StateOfTheArt/validate_tb.sh b/manual/CHAPTER_StateOfTheArt/validate_tb.sh similarity index 100% rename from manual/FILES_StateOfTheArt/validate_tb.sh rename to manual/CHAPTER_StateOfTheArt/validate_tb.sh -- 2.30.2