From 2cd5ac3019704485d5ab47529275de8d5c625693 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 9 Jun 2018 03:50:14 +0100 Subject: [PATCH] reorg --- simple_v_extension/simple_v_chennai_2018.tex | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index 0b9792f8c..22201be2d 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -244,7 +244,8 @@ \begin{itemize} \item Standard Register File(s) overloaded with CSR "reg is vector"\\ (see pseudocode slides for examples) - \item "2nd FP\&INT register bank" possibility (reserved for future) + \item "2nd FP\&INT register bank" possibility, reserved for future\\ + (would allow standard regfiles to remain unmodified) \item Element width concept remain same as RVV\\ (CSRs give new size to elements in registers) \item CSRs are key-value tables (overlaps allowed: v. important) @@ -389,6 +390,7 @@ def get\_pred\_val(bool is\_fp\_op, int reg): \begin{itemize} \item References different (internal) mapping table for INT or FP \item Actual predicate bitmask ALWAYS from the INT regfile + \item Hard-limit on MVL of XLEN (predication only 1 intreg) \end{itemize} \end{frame} -- 2.30.2