From 2cddf36aa2d86aac934868ec85054b564aae452c Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Oct 2018 03:38:33 +0100
Subject: [PATCH] combination of redirection through a "property" class
 overloads WRITE_RD

WRITE_RD, formerly a macro, now replaced with a function.
also required a redirector function rd
---
 riscv/insn_template_sv.cc |  1 +
 riscv/processor.cc        |  2 +-
 riscv/sv.cc               |  1 +
 riscv/sv_decode.h         |  4 +++-
 riscv/sv_insn_redirect.cc |  5 ++---
 riscv/sv_insn_redirect.h  | 19 ++++++++++++++++---
 6 files changed, 24 insertions(+), 8 deletions(-)

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index f815e07..f37eaa7 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -107,6 +107,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   bool zeroingtarg = false;
 #endif
   sv_insn_t insn(p, bits, floatintmap, PRED_ARGS, OFFS_ARGS);
+  p->s.insn = insn;
 #ifdef INSN_TYPE_BRANCH
   sv_pred_entry *r = insn.get_predentry(s_insn.rs2(), true);
   reg_t _target_reg = 0;
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 68128d2..0b6dcfa 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -27,7 +27,7 @@ processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id,
   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
 #ifdef SPIKE_SIMPLEV
-    , s()
+    , s(this)
 #endif
 {
   parse_isa_string(isa);
diff --git a/riscv/sv.cc b/riscv/sv.cc
index ba4fd53..4bc0f96 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -1,5 +1,6 @@
 #include "sv.h"
 #include "sv_decode.h"
+#include "processor.h"
 
 sv_pred_entry* sv_insn_t::get_predentry(uint64_t reg, bool intreg)
 {
diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 98252e7..8438f1c 100644
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -5,7 +5,7 @@
 
 #include "sv.h"
 #include "decode.h"
-#include "processor.h"
+//#include "processor.h"
 
 #define REG_RD 0x1
 #define REG_RS1 0x2
@@ -17,6 +17,8 @@
 #define REG_RVC_RS2S 0x80
 
 
+class processor_t;
+
 class sv_insn_t: public insn_t
 {
 public:
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 805ce74..85ed536 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -1,8 +1,7 @@
 #include "sv_insn_redirect.h"
+#include "processor.h"
 
-/*
-void (WRITE_RD)(reg_t value)
+void (sv_proc_t::WRITE_RD)(reg_t value)
 {
     WRITE_RD( value );
 }
-*/
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index bc2514e..ebdc607 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -2,15 +2,28 @@
 #define SV_INSN_REDIRECT_H
 
 #include "decode.h"
-
-//extern void (WRITE_RD)(reg_t value);
+#include "sv_decode.h"
 
 class processor_t;
+class insn_t;
 
 class sv_proc_t
 {
 public:
-    sv_proc_t() {}
+    sv_proc_t(processor_t *_p) : p(_p) {}
+    void (WRITE_RD)(reg_t value);
+
+    processor_t *p;
+
+    class {
+        public:
+        sv_insn_t *_insn;
+        sv_insn_t & operator = (sv_insn_t &i)
+        { _insn = &i; return i; }
+        operator sv_insn_t () const { return *_insn; }
+        uint64_t rd() { return _insn->rd(); }
+    } insn;
+
 #include "sv_insn_decl.h"
 };
 
-- 
2.30.2