From 2ce29ce5afbace43836fb55e8a5b5a989a222529 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Wed, 31 Dec 2014 02:15:23 -0500 Subject: [PATCH] i965/gen6+: enable EXT_polygon_offset_clamp Replace the hard-coded 0's with the context clamp value. Signed-off-by: Ilia Mirkin Reviewed-by: Kenneth Graunke --- docs/relnotes/10.5.0.html | 1 + src/mesa/drivers/dri/i965/gen6_sf_state.c | 2 +- src/mesa/drivers/dri/i965/gen7_sf_state.c | 2 +- src/mesa/drivers/dri/i965/gen8_sf_state.c | 2 +- src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 5 files changed, 5 insertions(+), 3 deletions(-) diff --git a/docs/relnotes/10.5.0.html b/docs/relnotes/10.5.0.html index 4f921ea4d5c..bf932d4a4ae 100644 --- a/docs/relnotes/10.5.0.html +++ b/docs/relnotes/10.5.0.html @@ -47,6 +47,7 @@ Note: some of the new features are only available with certain drivers.
  • GL_ARB_framebuffer_sRGB on freedreno
  • GL_ARB_texture_rg on freedreno
  • GL_EXT_packed_float on freedreno
    • +
  • GL_EXT_polygon_offset_clamp on i965
  • GL_EXT_texture_shared_exponent on freedreno
  • GL_EXT_texture_snorm on freedreno
    • diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c index fc73c572da7..7f0bab86c55 100644 --- a/src/mesa/drivers/dri/i965/gen6_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c @@ -427,7 +427,7 @@ upload_sf_state(struct brw_context *brw) OUT_BATCH(dw4); OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant. copied from gen4 */ OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */ - OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */ + OUT_BATCH_F(ctx->Polygon.OffsetClamp); /* global depth offset clamp */ for (i = 0; i < 8; i++) { OUT_BATCH(attr_overrides[i * 2] | attr_overrides[i * 2 + 1] << 16); } diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c index b9838470c64..6644010ca1b 100644 --- a/src/mesa/drivers/dri/i965/gen7_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c @@ -242,7 +242,7 @@ upload_sf_state(struct brw_context *brw) OUT_BATCH(dw3); OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant. copied from gen4 */ OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */ - OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */ + OUT_BATCH_F(ctx->Polygon.OffsetClamp); /* global depth offset clamp */ ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c b/src/mesa/drivers/dri/i965/gen8_sf_state.c index 0e514c61010..713ee5f93a0 100644 --- a/src/mesa/drivers/dri/i965/gen8_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c @@ -314,7 +314,7 @@ upload_raster(struct brw_context *brw) OUT_BATCH(dw1); OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant. copied from gen4 */ OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */ - OUT_BATCH_F(0.0); + OUT_BATCH_F(ctx->Polygon.OffsetClamp); /* global depth offset clamp */ ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 2187e734017..4dacfd09429 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -285,6 +285,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.ARB_texture_gather = true; ctx->Extensions.ARB_conditional_render_inverted = true; ctx->Extensions.AMD_vertex_shader_layer = true; + ctx->Extensions.EXT_polygon_offset_clamp = true; /* Test if the kernel has the ioctl. */ if (drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &dummy) == 0) -- 2.30.2