From 2d0a66cbc123fc345deb070c323130382518f367 Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Tue, 10 Feb 2009 15:49:29 -0800
Subject: [PATCH] CPU: Prepare CPU models for the new in-order CPU model. Some
 new functions and forward declarations are necessary to make things work

---
 src/cpu/SConscript     | 10 ++++++----
 src/cpu/o3/ras.hh      |  3 +++
 src/cpu/static_inst.hh | 11 ++++++++---
 3 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index f210cec9b..eee8edca4 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -48,12 +48,14 @@ execfile(models_db.srcnode().abspath)
 
 # Template for execute() signature.
 exec_sig_template = '''
-virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0;
-virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const
+virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
+virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
 { panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
-virtual Fault completeAcc(Packet *pkt, %s *xc,
+virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
                           Trace::InstRecord *traceData) const
 { panic("completeAcc not defined!"); M5_DUMMY_RETURN };
+virtual int memAccSize(%(type)s *xc)
+{ panic("memAccSize not defined!"); M5_DUMMY_RETURN };
 '''
 
 mem_ini_sig_template = '''
@@ -82,7 +84,7 @@ def gen_cpu_exec_signatures(target, source, env):
 '''
     for cpu in temp_cpu_list:
         xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
-        print >> f, exec_sig_template % (xc_type, xc_type, xc_type)
+        print >> f, exec_sig_template % { 'type' : xc_type }
     print >> f, '''
 #endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
 '''
diff --git a/src/cpu/o3/ras.hh b/src/cpu/o3/ras.hh
index 97846ed16..f0621c5b5 100644
--- a/src/cpu/o3/ras.hh
+++ b/src/cpu/o3/ras.hh
@@ -71,6 +71,9 @@ class ReturnAddrStack
      */
     void restore(unsigned top_entry_idx, const Addr &restored_target);
 
+     bool empty() { return usedEntries == 0; }
+
+     bool full() { return usedEntries == numEntries; }
   private:
     /** Increments the top of stack index. */
     inline void incrTos()
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 032a304ad..f28b53ccf 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -56,9 +56,8 @@ class Packet;
 class O3CPUImpl;
 template <class Impl> class BaseO3DynInst;
 typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
-
-template <class Impl>
-class OzoneDynInst;
+template <class Impl> class OzoneDynInst;
+class InOrderDynInst;
 
 class CheckerCPU;
 class FastCPU;
@@ -434,6 +433,12 @@ class StaticInst : public StaticInstBase
      */
     bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
 
+    virtual Request::Flags memAccFlags()
+    {
+        panic("StaticInst::memAccFlags called on non-memory instruction");
+        return 0;
+    };
+
     /**
      * Return string representation of disassembled instruction.
      * The default version of this function will call the internal
-- 
2.30.2