From 2d14da579356909b48d23a4bf8a2889a7a198e96 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 11 Jul 2020 11:08:48 +0100 Subject: [PATCH] special test for mul hw to cope with ignoring OE flag --- src/soc/decoder/isa/caller.py | 17 +++++++++--- src/soc/decoder/power_decoder2.py | 16 +++++++---- src/soc/fu/mul/test/test_pipe_caller.py | 36 +++++++++++++++++++++---- 3 files changed, 55 insertions(+), 14 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index ef6e46dd..3c3dcce5 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -506,16 +506,25 @@ class ISACaller: asmcode = yield self.dec2.dec.op.asmcode print ("get assembly name asmcode", asmcode) asmop = insns.get(asmcode, None) + int_op = yield self.dec2.dec.op.internal_op # sigh reconstruct the assembly instruction name ov_en = yield self.dec2.e.do.oe.oe ov_ok = yield self.dec2.e.do.oe.ok - if ov_en & ov_ok: - asmop += "." + rc_en = yield self.dec2.e.do.rc.data + rc_ok = yield self.dec2.e.do.rc.ok + # grrrr have to special-case MUL op (see DecodeOE) + print ("ov en rc en", ov_ok, ov_en, rc_ok, rc_en, int_op) + if int_op in [InternalOp.OP_MUL_H64.value, InternalOp.OP_MUL_H32.value]: + print ("mul op") + if rc_en & rc_ok: + asmop += "." + else: + if ov_en & ov_ok: + asmop += "." lk = yield self.dec2.e.do.lk if lk: asmop += "l" - int_op = yield self.dec2.dec.op.internal_op print ("int_op", int_op) if int_op in [InternalOp.OP_B.value, InternalOp.OP_BC.value]: AA = yield self.dec2.dec.fields.FormI.AA[0:-1] @@ -628,7 +637,7 @@ class ISACaller: ov_en = yield self.dec2.e.do.oe.oe ov_ok = yield self.dec2.e.do.oe.ok - print ("internal overflow", overflow) + print ("internal overflow", overflow, ov_en, ov_ok) if ov_en & ov_ok: yield from self.handle_overflow(inputs, results, overflow) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 20c40075..5ad8a89f 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -429,12 +429,18 @@ class DecodeOE(Elaboratable): def elaborate(self, platform): m = Module() comb = m.d.comb + op = self.dec.op - # select OE bit out field - with m.Switch(self.sel_in): - with m.Case(RC.RC): - comb += self.oe_out.data.eq(self.dec.OE) - comb += self.oe_out.ok.eq(1) + with m.If((op.internal_op == InternalOp.OP_MUL_H64) | + (op.internal_op == InternalOp.OP_MUL_H32)): + # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE + pass + with m.Else(): + # select OE bit out field + with m.Switch(self.sel_in): + with m.Case(RC.RC): + comb += self.oe_out.data.eq(self.dec.OE) + comb += self.oe_out.ok.eq(1) return m diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py index 44f5a09e..402bae87 100644 --- a/src/soc/fu/mul/test/test_pipe_caller.py +++ b/src/soc/fu/mul/test/test_pipe_caller.py @@ -107,7 +107,7 @@ class MulTestCase(FHDLTestCase): initial_regs[2] = 0xe self.run_tst_program(Program(lst), initial_regs) - def test_4_mullw_rand(self): + def tst_4_mullw_rand(self): for i in range(40): lst = ["mullw 3, 1, 2"] initial_regs = [0] * 32 @@ -115,7 +115,7 @@ class MulTestCase(FHDLTestCase): initial_regs[2] = random.randint(0, (1<<64)-1) self.run_tst_program(Program(lst), initial_regs) - def test_4_mullw_nonrand(self): + def tst_4_mullw_nonrand(self): for i in range(40): lst = ["mullw 3, 1, 2"] initial_regs = [0] * 32 @@ -123,8 +123,34 @@ class MulTestCase(FHDLTestCase): initial_regs[2] = i+20 self.run_tst_program(Program(lst), initial_regs) - def tst_rand_mullw(self): - insns = ["mullw", "mullw.", "mullwo", "mullwo."] + def test_mulhw__regression_1(self): + lst = ["mulhw. 3, 1, 2" + ] + initial_regs = [0] * 32 + initial_regs[1] = 0x7745b36eca6646fa + initial_regs[2] = 0x47dfba3a63834ba2 + self.run_tst_program(Program(lst), initial_regs) + + def tst_4_mullw_rand(self): + for i in range(40): + lst = ["mullw 3, 1, 2"] + initial_regs = [0] * 32 + initial_regs[1] = random.randint(0, (1<<64)-1) + initial_regs[2] = random.randint(0, (1<<64)-1) + self.run_tst_program(Program(lst), initial_regs) + + def tst_rand_mul_lh(self): + insns = ["mulhw", "mulhw.", "mulhwu", "mulhwu."] + for i in range(40): + choice = random.choice(insns) + lst = [f"{choice} 3, 1, 2"] + initial_regs = [0] * 32 + initial_regs[1] = random.randint(0, (1<<64)-1) + initial_regs[2] = random.randint(0, (1<<64)-1) + self.run_tst_program(Program(lst), initial_regs) + + def tst_rand_mullwu(self): + insns = ["mullwu", "mullwu.", "mullwuo", "mullwuo."] for i in range(40): choice = random.choice(insns) lst = [f"{choice} 3, 1, 2"] @@ -133,7 +159,7 @@ class MulTestCase(FHDLTestCase): initial_regs[2] = random.randint(0, (1<<64)-1) self.run_tst_program(Program(lst), initial_regs) - def test_ilang(self): + def tst_ilang(self): pspec = MulPipeSpec(id_wid=2) alu = MulBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) -- 2.30.2