From 2d2388f82f2e7f2fd1da063192ba98be45f099d2 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 15 Aug 2019 08:55:00 +0000 Subject: [PATCH] [AArch64] Tweak operand choice for SVE predicate AND SVE defines an assembly alias: MOV pa.B, pb/Z, pc.B -> AND pa.B. pb/Z, pc.B, pc.B Our and3 pattern was instead using the functionally-equivalent: AND pa.B. pb/Z, pb.B, pc.B ^^^^ This patch duplicates pc.B instead so that the alias can be seen in disassembly. I wondered about using the alias in the pattern instead, but using AND explicitly seems to fit better with the pattern name and surrounding code. 2019-08-15 Richard Sandiford gcc/ * config/aarch64/aarch64-sve.md (and3): Make the operand order match the MOV /Z alias. From-SVN: r274521 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/aarch64-sve.md | 4 +++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 873c265518a..917278ee07e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-08-15 Richard Sandiford + + * config/aarch64/aarch64-sve.md (and3): Make the + operand order match the MOV /Z alias. + 2019-08-15 Richard Sandiford * config/aarch64/aarch64.c (aarch64_output_sve_cnt_immediate): Take diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index f1f4fa26ba9..ac65e691d73 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -3317,12 +3317,14 @@ ;; ------------------------------------------------------------------------- ;; Predicate AND. We can reuse one of the inputs as the GP. +;; Doubling the second operand is the preferred implementation +;; of the MOV alias, so we use that instead of %1/z, %1, %2. (define_insn "and3" [(set (match_operand:PRED_ALL 0 "register_operand" "=Upa") (and:PRED_ALL (match_operand:PRED_ALL 1 "register_operand" "Upa") (match_operand:PRED_ALL 2 "register_operand" "Upa")))] "TARGET_SVE" - "and\t%0.b, %1/z, %1.b, %2.b" + "and\t%0.b, %1/z, %2.b, %2.b" ) ;; Unpredicated predicate EOR and ORR. -- 2.30.2