From 2d2e9b82f194df51bbb4ec27105ce7e97dd5f0bb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 17 May 2020 22:11:41 +0100 Subject: [PATCH] clarification on 6600 --- 3d_gpu/architecture/6600scoreboard.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3d_gpu/architecture/6600scoreboard.mdwn b/3d_gpu/architecture/6600scoreboard.mdwn index 8ad5c6835..0d5e1645e 100644 --- a/3d_gpu/architecture/6600scoreboard.mdwn +++ b/3d_gpu/architecture/6600scoreboard.mdwn @@ -75,7 +75,7 @@ ultimately then, there is: * an FU-FU Matrix that preserves, as a Directed Acyclic Graph (DAG), the instruction order.  again, this is a bit-based system (SR Latches) that record which *read port* of the Function Unit needs a write result - (when available). + (when available), and which write port needs a *read* result. * a suite of Function Units with input *and* output latches where the register information is *removed* (that being back in the FU-Regs row associated with a given FU) -- 2.30.2