From 2d2f227e1d95e428a51b230611ed42e02a7f8fe1 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Sun, 24 Jan 2021 17:01:24 +0000 Subject: [PATCH] arch-arm: Add set_reg_idx_arr to SveStructMemSIMicroopDeclare This should have been part of: https://gem5-review.googlesource.com/c/public/gem5/+/38381 Change-Id: I1914fdcd0382fc95dcead2eafa09de12a43776ab Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39635 Reviewed-by: Gabe Black Tested-by: kokoro --- src/arch/arm/isa/templates/sve_mem.isa | 1 + 1 file changed, 1 insertion(+) diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa index 8bfb423e3..f635870b0 100644 --- a/src/arch/arm/isa/templates/sve_mem.isa +++ b/src/arch/arm/isa/templates/sve_mem.isa @@ -911,6 +911,7 @@ def template SveStructMemSIMicroopDeclare {{ numRegs(_numRegs), regIndex(_regIndex), memAccessFlags(ArmISA::TLB::AllowUnaligned) { + %(set_reg_idx_arr)s; %(constructor)s; baseIsSP = isSP(_base); } -- 2.30.2