From 2d596569211c7bc262c54d31ada09fb540be2b98 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 15 Jun 2020 21:55:39 +0100 Subject: [PATCH] imports and syntax errors fixed (found test_cache.py) --- src/soc/minerva/cache.py | 2 +- src/soc/minerva/test/test_cache.py | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/minerva/cache.py b/src/soc/minerva/cache.py index 57b7ba55..dabcb3a7 100644 --- a/src/soc/minerva/cache.py +++ b/src/soc/minerva/cache.py @@ -73,8 +73,8 @@ class L1Cache(Elaboratable): hit = (way.tag == self.s2_addr.tag) & way.valid m.d.comb += way_hit.i[j].eq(hit) + rdata = ways[way_hit.o].data.word_select(self.s2_addr.offset, 32) m.d.comb += [ - rdata = ways[way_hit.o].data.word_select(self.s2_addr.offset, 32) self.s2_miss.eq(way_hit.n), self.s2_rdata.eq(rdata) ] diff --git a/src/soc/minerva/test/test_cache.py b/src/soc/minerva/test/test_cache.py index c56a465d..02e16e55 100644 --- a/src/soc/minerva/test/test_cache.py +++ b/src/soc/minerva/test/test_cache.py @@ -1,9 +1,9 @@ -from nmigen import * +from nmigen import Elaboratable, Module, Signal, Record from nmigen.utils import log2_int -from nmutil.formaltest import * -from nmigen.asserts import * +from nmutil.formaltest import FHDLTestCase +from nmigen.asserts import AnyConst, AnySeq, Assert, Assume, Past, Initial -from ..cache import L1Cache +from soc.minerva.cache import L1Cache class L1CacheSpec(Elaboratable): -- 2.30.2