From 2d785b67ed5d6de82ce956f10e31c87eabd97dc0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 3 Jul 2020 04:12:34 +0100 Subject: [PATCH] set only div/rem supported --- src/soc/fu/div/pipe_data.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py index ac3e434a..3a7f35d2 100644 --- a/src/soc/fu/div/pipe_data.py +++ b/src/soc/fu/div/pipe_data.py @@ -3,7 +3,7 @@ from soc.fu.pipe_data import IntegerData from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec from soc.fu.logical.logical_input_record import CompLogicalOpSubset from ieee754.div_rem_sqrt_rsqrt.core import ( - DivPipeCoreConfig, DivPipeCoreInputData, + DivPipeCoreConfig, DivPipeCoreInputData, DP, DivPipeCoreInterstageData, DivPipeCoreOutputData) @@ -24,6 +24,7 @@ class DIVPipeSpec(CommonPipeSpec): bit_width=64, fract_width=64, log2_radix=1, + supported=[DP.UDivRem] ) -- 2.30.2