From 2d785cb0ac535dbaa27e2d8c641c5e73fac39b24 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 24 Sep 2018 02:03:30 +0200
Subject: [PATCH] boards/plarforms: fix issues found while testing simple
 design on all platforms

---
 litex/boards/platforms/genesys2.py | 7 +++----
 litex/boards/platforms/mimasv2.py  | 1 -
 litex/boards/platforms/sim.py      | 1 -
 3 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py
index e8d8fc3b..0a454ab8 100644
--- a/litex/boards/platforms/genesys2.py
+++ b/litex/boards/platforms/genesys2.py
@@ -102,6 +102,9 @@ _connectors = [
 ]
 
 class Platform(XilinxPlatform):
+    default_clk_name = "clk200"
+    default_clk_period = 5
+
     def __init__(self, programmer="vivado"):
         XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
         self.programmer = programmer
@@ -114,7 +117,3 @@ class Platform(XilinxPlatform):
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
-        try:
-            self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
-        except ConstraintError:
-            pass
diff --git a/litex/boards/platforms/mimasv2.py b/litex/boards/platforms/mimasv2.py
index ec4c0614..b5352a11 100644
--- a/litex/boards/platforms/mimasv2.py
+++ b/litex/boards/platforms/mimasv2.py
@@ -121,7 +121,6 @@ _connectors = [
 
 
 class Platform(XilinxPlatform):
-    name = "mimasv2"
     default_clk_name = "clk100"
     default_clk_period = 10
 
diff --git a/litex/boards/platforms/sim.py b/litex/boards/platforms/sim.py
index ce1cd635..f0dc23c7 100644
--- a/litex/boards/platforms/sim.py
+++ b/litex/boards/platforms/sim.py
@@ -54,7 +54,6 @@ _io = [
 
 
 class Platform(SimPlatform):
-    is_sim = True
     default_clk_name = "sys_clk"
     default_clk_period = 1000  # on modern computers simulate at ~ 1MHz
 
-- 
2.30.2