From 2d7941da28e6b1cd7507ed96bb722b1e3206c172 Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Tue, 5 May 2020 13:39:52 -0400 Subject: [PATCH] Patch ieee128-lib-patch009b --- gcc/ChangeLog.meissner | 18 +++++++++++++ gcc/config/rs6000/rs6000-builtin.def | 11 ++++++++ gcc/config/rs6000/rs6000-call.c | 40 ++++++++++++++++++++++++++++ 3 files changed, 69 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 31ecbb7e958..5711054f3a4 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,21 @@ +2020-05-05 Michael Meissner + + (ieee128-lib-patch009b) + * config/rs6000/rs6000-builtin.def (scalar_extract_exptf): Add + long double versions of the float128 built-in functions. + (scalar_extract_sigtf): Likewise. + (scalar_test_neg_tf): Likewise. + (scalar_insert_exp_tf): Likewise. + (scalar_insert_exp_tfp): Likewise. + (scalar_cmp_exp_tf_gt): Likewise. + (scalar_cmp_exp_tf_lt): Likewise. + (scalar_cmp_exp_tf_eq): Likewise. + (scalar_cmp_exp_tf_unordered): Likewise. + * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Add + long double variants of the float128 built-in functions. + (rs6000_expand_builtin): Convert some more float128 built-in + functions into supporting long double + 2020-05-05 Michael Meissner (ieee128-lib-patch007b) diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 54f750c8384..e8961f24317 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -2154,8 +2154,11 @@ BU_P9V_64BIT_VSX_1 (VSESDP, "scalar_extract_sig", CONST, xsxsigdp) BU_FLOAT128_HW_VSX_1 (VSEEQP, "scalar_extract_expq", CONST, xsxexpqp_kf) BU_FLOAT128_HW_VSX_1 (VSESQP, "scalar_extract_sigq", CONST, xsxsigqp_kf) +BU_FLOAT128_HW_VSX_1 (VSEETF, "scalar_extract_exptf", CONST, xsxexpqp_tf) +BU_FLOAT128_HW_VSX_1 (VSESTF, "scalar_extract_sigtf", CONST, xsxsigqp_tf) BU_FLOAT128_HW_VSX_1 (VSTDCNQP, "scalar_test_neg_qp", CONST, xststdcnegqp_kf) +BU_FLOAT128_HW_VSX_1 (VSTDCNTF, "scalar_test_neg_tf", CONST, xststdcnegqp_tf) BU_P9V_VSX_1 (VSTDCNDP, "scalar_test_neg_dp", CONST, xststdcnegdp) BU_P9V_VSX_1 (VSTDCNSP, "scalar_test_neg_sp", CONST, xststdcnegsp) @@ -2173,6 +2176,8 @@ BU_P9V_64BIT_VSX_2 (VSIEDPF, "scalar_insert_exp_dp", CONST, xsiexpdpf) BU_FLOAT128_HW_VSX_2 (VSIEQP, "scalar_insert_exp_q", CONST, xsiexpqp_kf) BU_FLOAT128_HW_VSX_2 (VSIEQPF, "scalar_insert_exp_qp", CONST, xsiexpqpf_kf) +BU_FLOAT128_HW_VSX_2 (VSIETF, "scalar_insert_exp_tf", CONST, xsiexpqp_tf) +BU_FLOAT128_HW_VSX_2 (VSIETFF, "scalar_insert_exp_tfp", CONST, xsiexpqpf_tf) BU_P9V_VSX_2 (VSCEDPGT, "scalar_cmp_exp_dp_gt", CONST, xscmpexpdp_gt) BU_P9V_VSX_2 (VSCEDPLT, "scalar_cmp_exp_dp_lt", CONST, xscmpexpdp_lt) @@ -2184,7 +2189,13 @@ BU_P9V_VSX_2 (VSCEQPLT, "scalar_cmp_exp_qp_lt", CONST, xscmpexpqp_lt_kf) BU_P9V_VSX_2 (VSCEQPEQ, "scalar_cmp_exp_qp_eq", CONST, xscmpexpqp_eq_kf) BU_P9V_VSX_2 (VSCEQPUO, "scalar_cmp_exp_qp_unordered", CONST, xscmpexpqp_unordered_kf) +BU_P9V_VSX_2 (VSCETFGT, "scalar_cmp_exp_tf_gt", CONST, xscmpexpqp_gt_tf) +BU_P9V_VSX_2 (VSCETFLT, "scalar_cmp_exp_tf_lt", CONST, xscmpexpqp_lt_tf) +BU_P9V_VSX_2 (VSCETFEQ, "scalar_cmp_exp_tf_eq", CONST, xscmpexpqp_eq_tf) +BU_P9V_VSX_2 (VSCETFUO, "scalar_cmp_exp_tf_unordered", CONST, xscmpexpqp_unordered_tf) + BU_FLOAT128_HW_VSX_2 (VSTDCQP, "scalar_test_data_class_qp", CONST, xststdcqp_kf) +BU_FLOAT128_HW_VSX_2 (VSTDCTF, "scalar_test_data_class_tf", CONST, xststdcqp_tf) BU_P9V_VSX_2 (VSTDCDP, "scalar_test_data_class_dp", CONST, xststdcdp) BU_P9V_VSX_2 (VSTDCSP, "scalar_test_data_class_sp", CONST, xststdcsp) diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 68164b912f0..d58fd6ba153 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -4565,6 +4565,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 }, { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP, RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 }, + { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCTF, + RS6000_BTI_bool_int, RS6000_BTI_long_double, RS6000_BTI_INTSI, 0 }, { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP, RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 }, @@ -4572,6 +4574,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 }, { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP, RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 }, + { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCTF, + RS6000_BTI_bool_int, RS6000_BTI_long_double, RS6000_BTI_INTSI, 0 }, { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP, RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 }, @@ -4579,6 +4583,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 }, { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP, RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 }, + { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNTF, + RS6000_BTI_bool_int, RS6000_BTI_long_double, 0, 0 }, { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP, RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 }, @@ -4586,16 +4592,22 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 }, { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP, RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 }, + { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNTF, + RS6000_BTI_bool_int, RS6000_BTI_long_double, 0, 0 }, { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP, RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 }, { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP, RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 }, + { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEETF, + RS6000_BTI_UINTDI, RS6000_BTI_long_double, 0, 0 }, { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP, RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 }, { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP, RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 }, + { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESTF, + RS6000_BTI_UINTTI, RS6000_BTI_long_double, 0, 0 }, { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP, RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 }, @@ -4604,25 +4616,37 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP, RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 }, + { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIETF, + RS6000_BTI_long_double, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 }, { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 }, + { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIETFF, + RS6000_BTI_long_double, RS6000_BTI_long_double, RS6000_BTI_UINTDI, 0 }, { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEDPGT, RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEQPGT, RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, + { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCETFGT, + RS6000_BTI_INTSI, RS6000_BTI_long_double, RS6000_BTI_long_double, 0 }, { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEDPLT, RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEQPLT, RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, + { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCETFLT, + RS6000_BTI_INTSI, RS6000_BTI_long_double, RS6000_BTI_long_double, 0 }, { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEDPEQ, RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEQPEQ, RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, + { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCETFEQ, + RS6000_BTI_INTSI, RS6000_BTI_long_double, RS6000_BTI_long_double, 0 }, { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEDPUO, RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEQPUO, RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, + { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCETFUO, + RS6000_BTI_INTSI, RS6000_BTI_long_double, RS6000_BTI_long_double, 0 }, { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, @@ -11560,6 +11584,22 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break; case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break; case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break; + + case CODE_FOR_xscmpexpqp_eq_kf: + icode = CODE_FOR_xscmpexpqp_eq_tf; + break; + + case CODE_FOR_xscmpexpqp_lt_kf: + icode = CODE_FOR_xscmpexpqp_lt_tf; + break; + + case CODE_FOR_xscmpexpqp_gt_kf: + icode = CODE_FOR_xscmpexpqp_gt_tf; + break; + + case CODE_FOR_xscmpexpqp_unordered_kf: + icode = CODE_FOR_xscmpexpqp_unordered_tf; + break; } if (TARGET_DEBUG_BUILTIN) -- 2.30.2