From 2d81a292036445c440e56d07ce3d5294e0411d71 Mon Sep 17 00:00:00 2001 From: Connor Abbott Date: Mon, 29 Feb 2016 12:35:05 +0100 Subject: [PATCH] i965/vec4/nir: allocate two registers for dvec3/dvec4 v2 (Curro): - Do not special-case for a bit-size of 64, divide the bit_size by 32 instead. - Use DIV_ROUND_UP so we can handle sub-32-bit types. v3 (Ian): - Make num_regs const. Reviewed-by: Ian Romanick Reviewed-by: Matt Turner --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 7128ca71720..37c99268b5c 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp @@ -140,8 +140,8 @@ vec4_visitor::nir_emit_impl(nir_function_impl *impl) foreach_list_typed(nir_register, reg, node, &impl->registers) { unsigned array_elems = reg->num_array_elems == 0 ? 1 : reg->num_array_elems; - - nir_locals[reg->index] = dst_reg(VGRF, alloc.allocate(array_elems)); + const unsigned num_regs = array_elems * DIV_ROUND_UP(reg->bit_size, 32); + nir_locals[reg->index] = dst_reg(VGRF, alloc.allocate(num_regs)); } nir_ssa_values = ralloc_array(mem_ctx, dst_reg, impl->ssa_alloc); @@ -270,7 +270,8 @@ dst_reg vec4_visitor::get_nir_dest(const nir_dest &dest) { if (dest.is_ssa) { - dst_reg dst = dst_reg(VGRF, alloc.allocate(1)); + dst_reg dst = + dst_reg(VGRF, alloc.allocate(DIV_ROUND_UP(dest.ssa.bit_size, 32))); nir_ssa_values[dest.ssa.index] = dst; return dst; } else { -- 2.30.2