From 2d9ee48ab0f11492625d6f5fd53d707d4cfdde82 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 22 Apr 2020 14:08:06 +0100 Subject: [PATCH] mention misaligned exception; --- 3d_gpu/architecture/6600scoreboard.mdwn | 3 +++ 1 file changed, 3 insertions(+) diff --git a/3d_gpu/architecture/6600scoreboard.mdwn b/3d_gpu/architecture/6600scoreboard.mdwn index 99ad1fef8..c5a5ae8dd 100644 --- a/3d_gpu/architecture/6600scoreboard.mdwn +++ b/3d_gpu/architecture/6600scoreboard.mdwn @@ -359,6 +359,9 @@ Notes: * It does however mean that the reservation on the row has to wait for *both* ports (left and right) to clear out their LD/ST operation(s). * Addr[4] still selects whether the request is to go into left or right bank +* When the misaligned address bits 4-11 are all 0b11111111, this is not + a case that can be handled, because it implies that Addr[12:48] will + be **different** in the row. This case throws a misaligned exception. Other than that, the design remains the same, as does the algorithm to merge the bytemasks. This remains as follows: -- 2.30.2