From 2db667290a19d15122d8d0c011f4b813bb542bc5 Mon Sep 17 00:00:00 2001 From: Oliver McFadden Date: Wed, 9 May 2007 18:06:10 +0000 Subject: [PATCH] r300: Further reduced the diff between radeon_span.[ch]. --- src/mesa/drivers/dri/r300/radeon_span.c | 2 -- src/mesa/drivers/dri/radeon/radeon_span.c | 3 +++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/r300/radeon_span.c b/src/mesa/drivers/dri/r300/radeon_span.c index 9cae955de8b..8b20034b191 100644 --- a/src/mesa/drivers/dri/r300/radeon_span.c +++ b/src/mesa/drivers/dri/r300/radeon_span.c @@ -40,9 +40,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include #include "glheader.h" -#include "imports.h" #include "swrast/swrast.h" #include "r300_state.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 39452f8b4e7..fd7a8c4fbfc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -179,6 +179,9 @@ radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y) #include "depthtmp.h" /* 24 bit depth, 8 bit stencil depthbuffer functions + * + * Careful: It looks like the R300 uses ZZZS byte order while the R200 + * uses SZZZ for 24 bit depth, 8 bit stencil mode. */ #define WRITE_DEPTH( _x, _y, d ) \ do { \ -- 2.30.2