From 2dccddd26991ba90c60b16f8a8f0f6eff331713a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 20 May 2020 05:44:52 +0100 Subject: [PATCH] convert Logical to use new XER use of Data() --- src/soc/fu/logical/main_stage.py | 2 +- src/soc/fu/logical/test/test_pipe_caller.py | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py index f4fb3641..d8c3b2fb 100644 --- a/src/soc/fu/logical/main_stage.py +++ b/src/soc/fu/logical/main_stage.py @@ -131,7 +131,7 @@ class LogicalMainStage(PipeModBase): ###### sticky overflow and context, both pass-through ##### - comb += self.o.so.eq(self.i.so) + comb += self.o.xer_so.data.eq(self.i.so) comb += self.o.ctx.eq(self.i.ctx) return m diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index b4424521..6223a3dd 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -238,18 +238,18 @@ class TestRunner(FHDLTestCase): print(f"expected {expected:x}, actual: {alu_out:x}") self.assertEqual(expected, alu_out, code) yield from self.check_extra_alu_outputs(alu, pdecode2, - simulator) + simulator, code) sim.add_sync_process(process) with sim.write_vcd("simulator.vcd", "simulator.gtkw", traces=[]): sim.run() - def check_extra_alu_outputs(self, alu, dec2, sim): + def check_extra_alu_outputs(self, alu, dec2, sim, code): rc = yield dec2.e.rc.data if rc: cr_expected = sim.crl[0].get_range().value - cr_actual = yield alu.n.data_o.cr0 - self.assertEqual(cr_expected, cr_actual) + cr_actual = yield alu.n.data_o.cr0.data + self.assertEqual(cr_expected, cr_actual, code) if __name__ == "__main__": -- 2.30.2