From 2dd1842a67fe75c8705c1b9136f9d91defdc24cb Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Thu, 7 Nov 2019 09:45:01 +0000 Subject: [PATCH] arch-arm: Fix short descriptors cacheability during table walks This implies checking for the SCTLR.C bit TTBR1.IRGN0 bits. Change-Id: I341faf85692ce2d2b4afd30a2f4aabac0e133192 Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22724 Tested-by: kokoro --- src/arch/arm/table_walker.cc | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index ff4e67554..52e6be748 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -456,6 +456,15 @@ TableWalker::processWalk() { Addr ttbr = 0; + // For short descriptors, translation configs are held in + // TTBR1. + RegVal ttbr1 = currState->tc->readMiscReg(snsBankedIndex( + MISCREG_TTBR1, currState->tc, !currState->isSecure)); + + const auto irgn0_mask = 0x1; + const auto irgn1_mask = 0x40; + currState->isUncacheable = (ttbr1 & (irgn0_mask | irgn1_mask)) == 0; + // If translation isn't enabled, we shouldn't be here assert(currState->sctlr.m || isStage2); const bool is_atomic = currState->req->isAtomic(); @@ -505,8 +514,7 @@ TableWalker::processWalk() ArmFault::TranslationLL + L1, isStage2, ArmFault::VmsaTran); } - ttbr = currState->tc->readMiscReg(snsBankedIndex( - MISCREG_TTBR1, currState->tc, !currState->isSecure)); + ttbr = ttbr1; currState->ttbcr.n = 0; } @@ -533,7 +541,7 @@ TableWalker::processWalk() } Request::Flags flag = Request::PT_WALK; - if (currState->sctlr.c == 0) { + if (currState->sctlr.c == 0 || currState->isUncacheable) { flag.set(Request::UNCACHEABLE); } @@ -1545,6 +1553,11 @@ TableWalker::doL1Descriptor() } Request::Flags flag = Request::PT_WALK; + + if (currState->sctlr.c == 0 || currState->isUncacheable) { + flag.set(Request::UNCACHEABLE); + } + if (currState->isSecure) flag.set(Request::SECURE); -- 2.30.2