From 2de95a2d66340e617a7e94d61384b6d511e8a52a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 21 Oct 2018 17:16:41 +0100 Subject: [PATCH] analysing addiw, potential flaw in algorithm --- simple_v_extension/specification.mdwn | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index f5fc87d20..4adc449f0 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -1474,7 +1474,7 @@ where addw sign-extends. ### addw -Standard Scalar RV32/RV64 (xlen): +Standard Scalar RV64 (xlen): * RS1 @ xlen bits * RS2 @ xlen bits @@ -1491,8 +1491,33 @@ Polymorphic variant: Note here that polymorphic addw sign-extends its source operands, where add zero-extends. +This requires a little more in-depth analysis. Where the bitwidth of +rs1 equals the bitwidth of rs2, no sign-extending will occur. It is +only where the bitwidth of either rs1 or rs2 are different, will the +lesser-width operand be sign-extended. + +Effectively however, both rs1 and rs2 are being sign-extended to the +bitwidth of rd (or truncated), where for add they are both zero-extended. + TODO +### addiw + +Standard Scalar RV64I: + +* RS1 @ xlen bits, truncated to 32-bit +* immed @ 12 bits, sign-extended to 32-bit +* add @ 32 bits +* RD @ rd bits. sign-extend to rd if rd > 32, otherwise truncate. + +Polymorphic variant: + +* RS1 @ rs1 bits +* immed @ 12 bits, sign-extend to max(rs1, 12) bits +* add @ max(rs1, 12) bits +* RD @ rd bits. sign-extend to rd if rd > max(rs1, 12) otherwise truncate + + # Exceptions TODO: expand. Exceptions may occur at any time, in any given underlying -- 2.30.2