From 2e127592a7273ab34ef4970d183dc15bbab8257b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 27 Sep 2014 11:18:15 -0700 Subject: [PATCH] Avoid some unused variable warnings ...and also save some space by not defining the register names in a header. --- riscv/disasm.h | 15 ++------------- riscv/regnames.cc | 15 +++++++++++++++ riscv/riscv.mk.in | 5 +++-- 3 files changed, 20 insertions(+), 15 deletions(-) create mode 100644 riscv/regnames.cc diff --git a/riscv/disasm.h b/riscv/disasm.h index 58a518a..a8da066 100644 --- a/riscv/disasm.h +++ b/riscv/disasm.h @@ -8,19 +8,8 @@ #include #include -static const char* xpr_name[] = { - "zero", "ra", "s0", "s1", "s2", "s3", "s4", "s5", - "s6", "s7", "s8", "s9", "s10", "s11", "sp", "tp", - "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5", - "a6", "a7", "t0", "t1", "t2", "t3", "t4", "gp" -}; - -static const char* fpr_name[] = { - "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", - "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15", - "fv0", "fv1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", - "fa6", "fa7", "ft0", "ft1", "ft2", "ft3", "ft4", "ft5" -}; +extern const char* xpr_name[NXPR]; +extern const char* fpr_name[NFPR]; class arg_t { diff --git a/riscv/regnames.cc b/riscv/regnames.cc new file mode 100644 index 0000000..93cb736 --- /dev/null +++ b/riscv/regnames.cc @@ -0,0 +1,15 @@ +#include "disasm.h" + +const char* xpr_name[] = { + "zero", "ra", "s0", "s1", "s2", "s3", "s4", "s5", + "s6", "s7", "s8", "s9", "s10", "s11", "sp", "tp", + "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5", + "a6", "a7", "t0", "t1", "t2", "t3", "t4", "gp" +}; + +const char* fpr_name[] = { + "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", + "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15", + "fv0", "fv1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", + "fa6", "fa7", "ft0", "ft1", "ft2", "ft3", "ft4", "ft5" +}; diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index e9ca63f..f916bd1 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -35,8 +35,9 @@ riscv_srcs = \ cachesim.cc \ mmu.cc \ disasm.cc \ - extension.cc \ - rocc.cc \ + extension.cc \ + rocc.cc \ + regnames.cc \ $(riscv_gen_srcs) \ riscv_test_srcs = -- 2.30.2