From 2e54001fc1878e6909c5e871b278504add3bf9fc Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 25 Aug 2012 23:29:23 +0200
Subject: [PATCH] - fix Spi2Csr mistakes

---
 sim/tb_spi2Csr.py   | 46 +++++++++++++++++++++++----------------------
 spi2Csr/__init__.py | 21 ++++++++++++---------
 2 files changed, 36 insertions(+), 31 deletions(-)

diff --git a/sim/tb_spi2Csr.py b/sim/tb_spi2Csr.py
index 1750b59d..1f3a04cf 100644
--- a/sim/tb_spi2Csr.py
+++ b/sim/tb_spi2Csr.py
@@ -15,10 +15,12 @@ def get_bit(dat, bit):
 	return int(dat & (1<<bit) != 0)
 
 def spi_transactions():
-	yield TWrite(0xA5A5,1)
-	yield TWrite(0x5A5A,2)
-	yield TWrite(0xA5A5,3)
-	yield TWrite(0x5A5A,4)
+	yield TWrite(0x8000,0x00)
+	yield TWrite(0x8001,0x01)
+	yield TWrite(0x8002,0x02)
+	yield TWrite(0x8003,0x03)
+	for i in range(100):
+		yield None 
 
 class SpiMaster(PureSimulable):
 	def __init__(self, spi, generator):
@@ -45,30 +47,30 @@ class SpiMaster(PureSimulable):
 			
 					# Clk
 					if self.transaction_cnt%2:
-						s.wr(self.spi.spi_clk,1)
+						s.wr(self.spi.spi_clk, 1)
 					else:
-						s.wr(self.spi.spi_clk,0)
+						s.wr(self.spi.spi_clk, 0)
 
 					# Mosi Addr
-					if self.transaction_cnt < a_w*2-1:	
+					if self.transaction_cnt < a_w*2:	
 						bit = a_w-1-int((self.transaction_cnt)/2)					
-						data = get_bit(self.transaction.address,bit)
-						s.wr(self.spi.spi_mosi,data)
-
+						data = get_bit(self.transaction.address, bit)
+						s.wr(self.spi.spi_mosi, data)
 					# Mosi Data
-					if self.transaction_cnt > a_w*2 and self.transaction_cnt < a_w*2+d_w*2-1:	
+					elif self.transaction_cnt >= a_w*2 and self.transaction_cnt < a_w*2+d_w*2:
 						bit = d_w-1-int((self.transaction_cnt-a_w*2)/2)					
 						data = get_bit(self.transaction.data,bit)
-						s.wr(self.spi.spi_mosi,data)					
-
+						s.wr(self.spi.spi_mosi, data)						
+					else:
+						s.wr(self.spi.spi_mosi, 0)
 
 					# Cs_n
 					if self.transaction_cnt < a_w*2+d_w*2:
 						s.wr(self.spi.spi_cs_n,0)
 					else:
-						s.wr(self.spi.spi_cs_n,1)
-						s.wr(self.spi.spi_clk,0)
-						s.wr(self.spi.spi_mosi,0)
+						s.wr(self.spi.spi_cs_n, 1)
+						s.wr(self.spi.spi_clk, 0)
+						s.wr(self.spi.spi_mosi, 0)
 						self.transaction = None
 
 					# Incr transaction_cnt
@@ -76,12 +78,12 @@ class SpiMaster(PureSimulable):
 
 def main():
 	# Csr Slave
-	scratch_reg0 = RegisterField("scratch_reg0", 32, reset=0,access_dev=READ_ONLY)
-	scratch_reg1 = RegisterField("scratch_reg1", 32, reset=0,access_dev=READ_ONLY)
-	scratch_reg2 = RegisterField("scratch_reg3", 32, reset=0,access_dev=READ_ONLY)
-	scratch_reg3 = RegisterField("scratch_reg4", 32, reset=0,access_dev=READ_ONLY)
-	regs = [scratch_reg0,scratch_reg1,scratch_reg2,scratch_reg3]
-	bank0 = csrgen.Bank([scratch_reg0,],address=0x0000)
+	scratch_reg0 = RegisterField("scratch_reg0", 32, reset=0, access_dev=READ_ONLY)
+	scratch_reg1 = RegisterField("scratch_reg1", 32, reset=0, access_dev=READ_ONLY)
+	scratch_reg2 = RegisterField("scratch_reg3", 32, reset=0, access_dev=READ_ONLY)
+	scratch_reg3 = RegisterField("scratch_reg4", 32, reset=0, access_dev=READ_ONLY)
+	regs = [scratch_reg0, scratch_reg1, scratch_reg2, scratch_reg3]
+	bank0 = csrgen.Bank(regs,address=0x0000)
 
 	# Spi2Csr
 	spi2csr0 = spi2Csr.Spi2Csr(16,8)
diff --git a/spi2Csr/__init__.py b/spi2Csr/__init__.py
index 1bc187db..07ea10a1 100644
--- a/spi2Csr/__init__.py
+++ b/spi2Csr/__init__.py
@@ -12,10 +12,10 @@ class Spi2Csr :
 		self.csr = csr.Interface(self.d_width)
 		# Spi interface
 		self.spi_clk = Signal()
-		self.spi_cs_n = Signal()
+		self.spi_cs_n = Signal(reset=1)
 		self.spi_mosi = Signal()
 		self.spi_miso = Signal()
-		self.spi_int_n = Signal()
+		self.spi_int_n = Signal(reset=1)
 		
 	def get_fragment(self):
 		comb = []
@@ -82,14 +82,17 @@ class Spi2Csr :
 		last_b = Signal()
 		
 		comb +=[
-			first_b.eq(spi_cnt[0:bits_for(self.d_width)] == 0),
-			last_b.eq(spi_cnt[0:bits_for(self.d_width)] == 2**self.d_width-1)
+			first_b.eq(spi_cnt[0:bits_for(self.d_width)-1] == 0),
+			last_b.eq(spi_cnt[0:bits_for(self.d_width)-1] == 2**(bits_for(self.d_width)-1)-1)
 		]
 		sync +=[
-			If(spi_cnt >= self.a_width & first_b,
+			If((spi_cnt >= (self.a_width + self.d_width)) & first_b,
 				spi_we.eq(spi_addr[self.a_width-1] & ~spi_we_re_done),
 				spi_re.eq(~spi_addr[self.a_width-1] & ~spi_we_re_done),
 				spi_we_re_done.eq(1)
+			).Elif((spi_cnt >= self.a_width) & first_b,
+				spi_re.eq(~spi_addr[self.a_width-1] & ~spi_we_re_done),
+				spi_we_re_done.eq(1)
 			).Else(
 				spi_we.eq(0),
 				spi_re.eq(0),
@@ -104,15 +107,15 @@ class Spi2Csr :
 			).Elif(spi_clk_rising,
 				# addr
 				If(spi_cnt < self.a_width,
-					spi_addr.eq(spi_addr[0:self.a_width-1]&spi_mosi_dat)
-				).Elif(spi_cnt >= self.a_width+self.d_width & last_b,
+					spi_addr.eq(Cat(spi_mosi_dat,spi_addr[:self.a_width-1]))
+				).Elif((spi_cnt >= (self.a_width+self.d_width)) & last_b,
 					spi_addr.eq(spi_addr+1)
-				).Elif(spi_cnt >= self.a_width & last_b & spi_cnt[self.a_width-1] == 0,
+				).Elif((spi_cnt >= self.a_width) & last_b & (spi_cnt[self.a_width-1] == 0),
 					spi_addr.eq(spi_addr+1)
 				),
 				# dat
 				If(spi_cnt >= self.a_width,
-					spi_w_dat.eq(Cat(spi_w_dat[:self.d_width],spi_mosi_dat))
+					spi_w_dat.eq(Cat(spi_mosi_dat,spi_w_dat[:self.d_width-1]))
 				),
 				
 				# spi_cnt
-- 
2.30.2